core.v

q6805.zip

endmodule // dadrs

`endif

`ifdef pc
`else
`define pc
module pc( CLK , DIS_PC, DIS_PC_TRK, DP, DP_RAW, EN_IACK, FRST_WRD, IF, IRQ,
           LD_PC_NOT, LD_PC_TRK, MFUNC, MON_ADRS, MRTI, MUL, MULE, NMI, READY,
           RESET, RESTOR, SBRK, SEL_DPZERO, SEL_MON_ADRS, SEL_STK, SEL_VECT,
           SEQ_CMPLT, STAK, SWI, VECTOR, XCLK_L, BRK_INSRVC, BRK_PND, INT_SEQ,
           IRQ_DET, PC, PC_DLY, RESET_DEL, RESET_SEQ );
output BRK_INSRVC, BRK_PND;
input CLK, DIS_PC, DIS_PC_TRK;
 input [15:0] DP;
 input [15:0] DP_RAW;
input EN_IACK, FRST_WRD, IF;
output INT_SEQ;
 input [5:0] IRQ;
output IRQ_DET;
input LD_PC_NOT, LD_PC_TRK, MFUNC;
 input [15:0] MON_ADRS;
input MRTI, MUL, MULE, NMI;
 output [15:0] PC;
 output [15:0] PC_DLY;
input READY, RESET;
output RESET_DEL, RESET_SEQ;
input RESTOR, SBRK, SEL_DPZERO, SEL_MON_ADRS, SEL_STK, SEL_VECT, SEQ_CMPLT;
 input [15:0] STAK;
input SWI;
 input [15:5] VECTOR;
input XCLK_L;

reg RESET_DEL;
reg	[15:0] PC;
reg [15:0] PC_DLY;
reg [15:0] PC_IN;

wire [15:0] MSD;
wire [15:0] M_STK;
wire [15:0] VECT;
wire N_7;
wire IRQ5_MUL;
wire N_3;
wire N_4;
supply0 GND;

assign IRQ5_MUL = (MULE & XCLK_L) ? MUL : IRQ[5];
assign N_3 = SEL_DPZERO | SEL_STK | SEL_MON_ADRS | RESET | SEL_VECT;
assign N_4 = SEL_DPZERO | SEL_STK | SEL_MON_ADRS | RESTOR;
assign MSD = SEL_STK ? STAK : MON_ADRS;
assign M_STK = SEL_DPZERO ? DP_RAW : MSD;
wire [1:0] MUX_SEL = {N_4, N_3};
always @(MUX_SEL or DP or VECT or PC_DLY or M_STK) begin
	casex (MUX_SEL) 
		2'b00 : PC_IN = DP;
		2'b01 : PC_IN = VECT;
		2'b10 : PC_IN = PC_DLY;
		2'b11 : PC_IN = M_STK;
		default : PC_IN = 16'bx;
	endcase
end

always @(posedge CLK ) begin
	if (READY) RESET_DEL <= RESET;
end

always @(posedge CLK) begin
	PC <= (READY & ~DIS_PC & ~ LD_PC_NOT) ? PC_IN : ((READY & ~DIS_PC) ? PC + 1 : PC);
end

always @(posedge CLK) begin
	PC_DLY <= (LD_PC_TRK & READY & ~DIS_PC_TRK) ? PC_IN : ((READY & ~DIS_PC_TRK) ? PC_DLY + 1 : PC_DLY);
end


vect I_1 ( .BRK_IN_SRVC(BRK_INSRVC), .BRK_PND(BRK_PND), .CLK(CLK),
        .EN_IACK(EN_IACK), .FRST_WRD(FRST_WRD), .IF(IF), .INT_SEQ(INT_SEQ),
        .IRQ({ IRQ5_MUL,IRQ[4:0] }), .IRQ_DET(IRQ_DET), .MFUNC(MFUNC),
        .MRTI(MRTI), .NMI(NMI), .READY(READY), .RESET(RESET),
        .RESET_SEQ(RESET_SEQ), .SBRK(SBRK), .SEQ_CMPLT(SEQ_CMPLT), .SWI(SWI),
        .VECT({ VECT[15:0] }), .VECTOR({ VECTOR[15:5] }), .XCLK_L(XCLK_L) );

endmodule // pc

`endif


`ifdef u_seqncr
`else
`define u_seqncr
module u_seqncr( ADC , ADD, AND, ASR, BIT, BRK_PND, BSC, BTB, BTB_TST, CCR, CLC,
                 CLI, CLR, CMP, COM, CPU_CLK, CPX, DEC, DIR3, DIRB, EOR, EXT,
                 IMM, INC, INH4, INH5, INH8, INH9, INT_SEQ, INT_STAT, INVALID,
                 IRQ, IX16, IX1E, IX2D, IX7, IXF, JMP, JSR, LDA, LDX, LOI,
                 LSL, LSR, MFUNC, MRD, MRET, MRTI, MUL, MULE, MWR, NEG, NOP,
                 OPCOD, ORA, REL, RESET_DEL, ROL, ROR, RSP, RST_SEQ, RTI, RTS,
                 SBC, SBRK, SEC, SEI, STA, STATE, STOP, STX, SUB, SWI, TAX,
                 TST, TXA, WAIT, WORM, ACC_SRC_SEL0, ACC_SRC_SEL1, ADD_1_PC,
                 ADD_ALU, ALU_OP_0, ALU_OP_1, AND_ALU, BSC_ST2, CF_SEL0,
                 CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLR_BT, CLR_DP_H,
                 CLR_DP_L, COMPL_A, DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD,
                 DIS_STATE, DISCNTY, EN_ACC, EN_CF, EN_DP_H, EN_HC, EN_IACK,
                 EN_IF, EN_MREG, EN_NF, EN_STK_PTR, EN_WR, EN_XREG, EN_ZF,
                 IF_SEL0, IF_SEL1, LD_ACC, LD_MREG, LD_PC_NOT, LD_PC_TRK,
                 LD_XREG, NEG_ADND, NEG_ONE, NF_SEL0, NF_SEL1, OUT_CCR,
                 OUT_MON, OUT_MREG, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP,
                 RESTOR, RTI_STB3, SEL_BOOL, SEL_DB, SEL_FF_00, SEL_MEM_A,
                 SEL_MON_ADRS, SEL_STK_PTR, SEL_VECT, SEL_XREG_A, SEQ_CMPLT,
                 SUB_ALU, X_SRC_SEL0, X_SRC_SEL1, ZERO, ZF_SEL0, ZF_SEL1 );
output ACC_SRC_SEL0, ACC_SRC_SEL1;
input ADC, ADD;
output ADD_1_PC, ADD_ALU, ALU_OP_0, ALU_OP_1;
input AND;
output AND_ALU;
input ASR, BIT, BRK_PND, BSC;
output BSC_ST2;
input BTB, BTB_TST;
 input [4:0] CCR;
output CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4;
input CLC, CLI, CLR;
output CLR_BT, CLR_DP_H, CLR_DP_L;
input CMP, COM;
output COMPL_A;
input CPU_CLK, CPX, DEC, DIR3, DIRB;
output DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD, DIS_STATE, DISCNTY, EN_ACC,
EN_CF, EN_DP_H, EN_HC, EN_IACK, EN_IF, EN_MREG, EN_NF, EN_STK_PTR,
EN_WR, EN_XREG, EN_ZF;
input EOR, EXT;
output IF_SEL0, IF_SEL1;
input IMM, INC, INH4, INH5, INH8, INH9, INT_SEQ;
 input [9:0] INT_STAT;
input INVALID, IRQ, IX16, IX1E, IX2D, IX7, IXF, JMP, JSR;
output LD_ACC, LD_MREG, LD_PC_NOT, LD_PC_TRK, LD_XREG;
input LDA, LDX, LOI, LSL, LSR, MFUNC, MRD, MRET, MRTI, MUL, MULE, MWR, NEG;
output NEG_ADND, NEG_ONE, NF_SEL0, NF_SEL1;
input NOP;
 input [3:0] OPCOD;
input ORA;
output OUT_CCR, OUT_MON, OUT_MREG, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP;
input REL, RESET_DEL;
output RESTOR;
input ROL, ROR, RSP, RST_SEQ, RTI;
output RTI_STB3;
input RTS, SBC, SBRK, SEC, SEI;
output SEL_BOOL, SEL_DB, SEL_FF_00, SEL_MEM_A, SEL_MON_ADRS, SEL_STK_PTR,
SEL_VECT, SEL_XREG_A, SEQ_CMPLT;
input STA;
 input [9:1] STATE;
input STOP, STX, SUB;
output SUB_ALU;
input SWI, TAX, TST, TXA, WAIT, WORM;
output X_SRC_SEL0, X_SRC_SEL1, ZERO, ZF_SEL0, ZF_SEL1;
wire BTB_DSCNTY;
wire BTB_STB3;
wire BTB_STB2;
wire BTB_STB1;
wire BSC_ST3;
wire BSC_ST1;
wire REL_STB1;
wire ADD_1_PC_f;
wire X_SRC_SEL0_f;
wire ACC_SRC_SEL0_f;
wire AND_ALU_e;
wire ADD_ALU_e;
wire LD_PC_TRK_f;
wire EN_NF_e;
wire PC_XREG_f;
wire NEG_ADND_f;
wire CLR_DP_L_f;
wire ZF_SEL0_f;
wire NF_SEL0_f;
wire DISCNTY_f;
wire CF_SEL0_f;
wire DIS_PC_f;
wire DIS_STATE_f;
wire LD_XREG_f;
wire LD_ACC_f;
wire SUB_A_f;
wire EN_WR_f;
wire DIS_RD_f;
wire EN_NF_f;
wire EN_ZF_f;
wire X_SRC_SEL1_f;
wire ACC_SRC_SEL1_f;
wire SEL_XREG_A_f;
wire SEL_FF_00_f;
wire SEL_BOOL_f;
wire CF_SEL1_f;
wire CF_SEL2_f;
wire CF_SEL3_f;
wire CF_SEL4_f;
wire EN_CF_f;
wire RESTOR_f;
wire ZERO_f;
wire SEQ_CMPLT_f;
wire DIS_FTCH_f;
wire EN_XREG_f;
wire EN_ACC_f;
wire CLR_DP_H_f;
wire DIS_PC_TRK_f;
wire LD_PC_f;
wire DIS_PC_e;
wire DIS_STATE_e;
wire SEL_BOOL_e;
wire CLR_DP_L_e;
wire CLR_DP_H_e;
wire ZERO_e;
wire LD_PC_e;
wire DIS_FTCH_e;
wire DIS_RD_e;
wire SEL_DB_e;
wire EN_MREG_e;
wire LD_MREG_e;
wire SEL_XREG_A_e;
wire DIS_PC_TRK_e;
wire EN_WR_e;
wire RESTORE_e;
wire OUT_MREG_e;
wire SEQ_CMPLT_e;
wire EN_ACCUM_e;
wire LD_ACCUM_e;
wire EN_XREG_e;
wire LD_XREG_e;
wire SEL_FF_00_e;
wire SUB_ALU_e;
wire CF_SEL0_e;
wire CF_SEL1_e;
wire CF_SEL2_e;
wire CF_SEL3_e;
wire CF_SEL4_e;
wire ZF_SEL1_e;
wire NF_SEL1_e;
wire ZF_SEL0_e;
wire NF_SEL0_e;
wire CLR_NF_e;
wire SET_ZF_e;
wire EN_C_e;
wire EN_Z_e;
wire DIS_PC_TRK_c;
wire SEQ_CMPLT_d;
wire DIS_FTCH_c;
wire LD_PC_c;
wire OUT_MREG_c;
wire CLR_DP_H_B;
wire LD_PC_B;



assign LD_PC_NOT = ~(RESET_DEL | LD_PC_B | LD_PC_c | REL_STB1 | LD_PC_e | LD_PC_f); 
assign X_SRC_SEL0 = LDX | X_SRC_SEL0_f;
assign ACC_SRC_SEL0 = LDA | ACC_SRC_SEL0_f;
assign ADD_ALU = ADD | ADD_ALU_e;
assign SEL_BOOL = SEL_BOOL_e | SEL_BOOL_f;
assign SEL_FF_00 = SEL_FF_00_e | SEL_FF_00_f;
assign SEL_XREG_A = SEL_XREG_A_e | SEL_XREG_A_f;
assign NF_SEL1 = NF_SEL1_e | RTI_STB3;
assign EN_NF = EN_NF_e | EN_NF_f;
assign CLR_BT = CLR_NF_e | SET_ZF_e;
assign ZF_SEL0 = ZF_SEL0_e | ZF_SEL0_f;
assign ZF_SEL1 = ZF_SEL1_e | RTI_STB3;
assign EN_ZF = EN_Z_e | EN_ZF_f;
assign NF_SEL0 = NF_SEL0_e | NF_SEL0_f;
assign EN_MREG = BSC_ST2 | EN_MREG_e;
assign CLR_DP_L = CLR_DP_L_e | CLR_DP_L_f;
assign DIS_STATE = DIS_STATE_e | DIS_STATE_f;
assign LD_XREG = LD_XREG_e | LD_XREG_f;
assign EN_XREG = EN_XREG_e | EN_XREG_f;
assign LD_ACC = LD_ACCUM_e | LD_ACC_f;
assign EN_ACC = EN_ACCUM_e | EN_ACC_f;
assign OUT_MREG = OUT_MREG_c | OUT_MREG_e;
assign CLR_DP_H = CLR_DP_H_B | BSC_ST1 | REL_STB1 | CLR_DP_H_e | CLR_DP_H_f;
assign SEQ_CMPLT = BTB_STB3 | BSC_ST3 | SEQ_CMPLT_d | SEQ_CMPLT_e | SEQ_CMPLT_f;
assign AND_ALU = BIT | AND | AND_ALU_e;
assign DISCNTY = BTB_DSCNTY | REL_STB1 | DISCNTY_f;
assign ADD_1_PC = REL_STB1 | BTB_STB3 | ADD_1_PC_f;
assign SUB_ALU = SUB | SUB_ALU_e | SUB_A_f;
assign ACC_SRC_SEL1 = LDA | MUL | ACC_SRC_SEL1_f;
assign X_SRC_SEL1 = LDX | MUL | X_SRC_SEL1_f;
assign LD_PC_TRK = REL_STB1 | BTB_DSCNTY | LD_PC_TRK_f;
assign LD_MREG = BTB_STB2 | BSC_ST2 | LD_MREG_e;
assign CF_SEL0 = BTB_STB2 | CF_SEL0_e | CF_SEL0_f;
assign CF_SEL1 = BTB_STB2 | CF_SEL1_e | CF_SEL1_f;
assign CF_SEL2 = BTB_STB2 | CF_SEL2_e | CF_SEL2_f;
assign EN_CF = BTB_STB2 | EN_C_e | EN_CF_f;
assign SEL_DB = BTB_STB2 | BSC_ST2 | SEL_DB_e;
assign CF_SEL4 = CF_SEL4_e | BTB_STB2 | CF_SEL4_f; 
assign CF_SEL3 = CF_SEL3_e | BTB_STB2 | CF_SEL3_f;
assign EN_WR = BSC_ST2 | EN_WR_e | EN_WR_f;
assign DIS_RD = BSC_ST2 | DIS_RD_e | DIS_RD_f;
assign DIS_PC = DIS_PC_e | BSC_ST2 | DIS_PC_f;
assign NEG_ADND = BTB_STB3 | REL_STB1 | NEG_ADND_f;
assign PC_XREG = BTB_STB3 | REL_STB1 | PC_XREG_f;
assign DIS_FTCH = BTB_STB1 | DIS_FTCH_c | DIS_FTCH_e | DIS_FTCH_f;
assign ZERO = BTB_STB1 | BSC_ST1 | ZERO_e | ZERO_f;
assign RESTOR = BTB_STB2 | BSC_ST3 | RESTORE_e | RESTOR_f;
assign DIS_PC_TRK = BTB_STB2 | DIS_PC_TRK_c | DIS_PC_TRK_e | DIS_PC_TRK_f;


othr_seq I_99 ( .ACC_SRC_SEL0(ACC_SRC_SEL0_f), .ACC_SRC_SEL1(ACC_SRC_SEL1_f),
             .ADC(ADC), .ADD(ADD), .ADD_1_PC(ADD_1_PC_f), .AND(AND), .BIT(BIT),
             .BRK_PND(BRK_PND), .CF_SEL0(CF_SEL0_f), .CF_SEL1(CF_SEL1_f),
             .CF_SEL2(CF_SEL2_f), .CF_SEL3(CF_SEL3_f), .CF_SEL4(CF_SEL4_f),
             .CLC(CLC), .CLI(CLI), .CLR_DP_H(CLR_DP_H_f),
             .CLR_DP_L(CLR_DP_L_f), .CMP(CMP), .CPU_CLK(CPU_CLK), .CPX(CPX),
             .DIRB(DIRB), .DIS_FTCH(DIS_FTCH_f), .DIS_PC(DIS_PC_f),
             .DIS_PC_TRK(DIS_PC_TRK_f), .DIS_RD(DIS_RD_f),
             .DIS_STATE(DIS_STATE_f), .DISCNTY(DISCNTY_f), .EN_ACC(EN_ACC_f),
             .EN_CF(EN_CF_f), .EN_DP_H(EN_DP_H), .EN_HC(EN_HC),
             .EN_IACK(EN_IACK), .EN_IF(EN_IF), .EN_NF(EN_NF_f),
             .EN_STK_PTR(EN_STK_PTR), .EN_WR(EN_WR_f), .EN_XREG(EN_XREG_f),
             .EN_ZF(EN_ZF_f), .EOR(EOR), .EXT(EXT), .IF_SEL0(IF_SEL0),
             .IF_SEL1(IF_SEL1), .IMM(IMM), .INT_SEQ(INT_SEQ),
             .INT_STAT({ INT_STAT[9:0] }), .INT_STB7(OUT_CCR),
             .INVALID(INVALID), .IX1E(IX1E), .IX2D(IX2D), .IXF(IXF), .JMP(JMP),
             .JSR(JSR), .LD_ACC(LD_ACC_f), .LD_PC(LD_PC_f),
             .LD_PC_TRK(LD_PC_TRK_f), .LD_XREG(LD_XREG_f), .LDA(LDA),
             .LDX(LDX), .LOI(LOI), .MFUNC(MFUNC), .MRD(MRD), .MRET(MRET),
             .MRTI(MRTI), .MUL(MUL), .MULE(MULE), .MWR(MWR),
             .NEG_ADND(NEG_ADND_f), .NEG_ONE(NEG_ONE), .NF_SEL0(NF_SEL0_f),
             .NOP(NOP), .ORA(ORA), .OUT_MON(OUT_MON), .OUT_PCH(OUT_PCH),
             .OUT_PCL(OUT_PCL), .OUT_XREG(OUT_XREG), .PC_XREG(PC_XREG_f),
             .POP(POP), .RESET(RESET_DEL), .RESTOR(RESTOR_f), .RSP(RSP),
             .RST_SEQ(RST_SEQ), .RTI(RTI), .RTI_STB3(RTI_STB3), .RTS(RTS),
             .SBC(SBC), .SBRK(SBRK), .SEC(SEC), .SEI(SEI),
             .SEL_BOOL(SEL_BOOL_f), .SEL_FF_00(SEL_FF_00_f),
             .SEL_MON_ADRS(SEL_MON_ADRS), .SEL_STK_PTR(SEL_STK_PTR),
             .SEL_VECT(SEL_VECT), .SEL_XREG_A(SEL_XREG_A_f),
             .SEQ_CMPLT(SEQ_CMPLT_f), .STA(STA), .STATE({ STATE[9:1] }),
             .STOP(STOP), .STX(STX), .SUB(SUB), .SUB_A(SUB_A_f), .SWI(SWI),
             .TAX(TAX), .TXA(TXA), .WAIT(WAIT), .WORM(WORM),
             .X_SRC_SEL0(X_SRC_SEL0_f), .X_SRC_SEL1(X_SRC_SEL1_f),
             .ZERO(ZERO_f), .ZF_SEL0(ZF_SEL0_f) );
dir3 I_92 ( .ADD_ALU(ADD_ALU_e), .ALU_OP_0(ALU_OP_0), .ALU_OP_1(ALU_OP_1),
         .AND_ALU(AND_ALU_e), .ASR(ASR), .CF_SEL0(CF_SEL0_e),
         .CF_SEL1(CF_SEL1_e), .CF_SEL2(CF_SEL2_e), .CF_SEL3(CF_SEL3_e),
         .CF_SEL4(CF_SEL4_e), .CLR(CLR), .CLR_DP_H(CLR_DP_H_e),
         .CLR_DP_L(CLR_DP_L_e), .CLR_NF(CLR_NF_e), .COM(COM),
         .COMPL_A(COMPL_A), .DEC(DEC), .DIR3(DIR3), .DIS_FTCH(DIS_FTCH_e),
         .DIS_PC(DIS_PC_e), .DIS_PC_TRK(DIS_PC_TRK_e), .DIS_RD(DIS_RD_e),
         .DIS_STATE(DIS_STATE_e), .EN_ACCUM(EN_ACCUM_e), .EN_C(EN_C_e),
         .EN_MREG(EN_MREG_e), .EN_N(EN_NF_e), .EN_WR(EN_WR_e),
         .EN_XREG(EN_XREG_e), .EN_Z(EN_Z_e), .INC(INC), .INH4(INH4),
         .INH5(INH5), .IX16(IX16), .IX7(IX7), .LD_ACCUM(LD_ACCUM_e),
         .LD_MREG(LD_MREG_e), .LD_PC(LD_PC_e), .LD_XREG(LD_XREG_e), .LSL(LSL),
         .LSR(LSR), .MUL(MUL), .NEG(NEG), .NF_SEL0(NF_SEL0_e),
         .NF_SEL1(NF_SEL1_e), .OUT_MREG(OUT_MREG_e), .RESTORE(RESTORE_e),
         .ROL(ROL), .ROR(ROR), .SEL_BOOL(SEL_BOOL_e), .SEL_DB(SEL_DB_e),
         .SEL_FF_00(SEL_FF_00_e), .SEL_MEM_A(SEL_MEM_A),
         .SEL_XREG_A(SEL_XREG_A_e), .SEQ_CMPLT(SEQ_CMPLT_e),
         .SET_ZF(SET_ZF_e), .STATE({ STATE[4:1] }), .SUB_ALU(SUB_ALU_e),
         .TST(TST), .ZERO(ZERO_e), .ZF_SEL0(ZF_SEL0_e), .ZF_SEL1(ZF_SEL1_e) );
rel_seq I_87 ( .CY(CCR[0]), .HC(CCR[4]), .IF(CCR[3]), .IRQ(IRQ), .N(CCR[2]),
            .OPCOD({ OPCOD[3:0] }), .REL(REL), .REL_STB1(REL_STB1),
            .SEQ_CMPLT(SEQ_CMPLT_d), .STATE_1(STATE[1]), .Z(CCR[1]) );
bsc I_86 ( .BSC(BSC), .BSC_ST1(BSC_ST1), .BSC_ST2(BSC_ST2), .BSC_ST3(BSC_ST3),
        .DIS_FTCH(DIS_FTCH_c), .DIS_PC_TRK(DIS_PC_TRK_c), .LD_PC(LD_PC_c),
        .OUT_MREG(OUT_MREG_c), .STATE({ STATE[3:1] }) );
btb_seq I_83 ( .BTB(BTB), .BTB_DSCNTY(BTB_DSCNTY), .BTB_STB1(BTB_STB1),
            .BTB_STB2(BTB_STB2), .BTB_STB3(BTB_STB3), .BTB_TST(BTB_TST),
            .CLR_DP_H(CLR_DP_H_B), .LD_PC(LD_PC_B), .STATE({ STATE[3:1] }) );

endmodule // u_seqncr

`endif

`ifdef decode
`else
`define decode
module decode( BRK_IN_SRVC , CLK, DIS_STATE, FETCH, FRST_WRD, INSTR, INT_SEQ, MFUNC_REQ,
               MON_INST, READY, RESET, RST_SEQ, SEQ_CMPLT, UDAT_STAT, ADC,
               ADD, AND, ASR, BIT, BRK_CMPLT, BSC, BTB, CLC, CLI, CLR, CMP,
               COM, CPX, DB_MXD, DEC, DECODE, DIR3, DIRB, EOR, EXT, IMM, INC,
               INH4, INH5, INH8, INH9, INT_STAT, INVALID, IX16, IX1E, IX2D,
               IX7, IXF, JMP, JSR, LDA, LDX, LOI, LSL, LSR, MFUNC,
               MON_CYC_CMPLT, MON_IN_SRVC, MRD, MRET, MRTI, MSR_CMPLT, MUL,
               MWR, NEG, NOP, ONE_CYC, OPCOD, ORA, REL, ROL, ROR, RSP, RTI,
               RTS, SBC, SBRK, SEC, SEI, STA, STATE, STOP, STX, SUB, SWI, TAX,
               TST, TXA, WAIT, WORM );
output ADC, ADD, AND, ASR, BIT, BRK_CMPLT;
input BRK_IN_SRVC;
output BSC, BTB, CLC, CLI;
input CLK;
output CLR, CMP, COM, CPX;
 output [7:0] DB_MXD;
output DEC, DECODE, DIR3, DIRB;
input DIS_STATE;
output EOR, EXT;