📄 core.v
字号:
ADD_1_PC, ADD_ALU, ALU_OP_0, ALU_OP_1, AND_ALU, BRK_CMPLT,
CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLC, CLR_BT,
CLR_DP_H, CLR_DP_L, COM, COMPL_A, DB_MXD, DECODE, DIS_FTCH,
DIS_PC, DIS_PC_TRK, DIS_RD, DISCNTY, EN_ACC, EN_BSC, EN_CF,
EN_DP_H, EN_HC, EN_IACK, EN_IF, EN_MREG, EN_NF, EN_STK_PTR,
EN_WR, EN_ZF, EOR, HC_SEL0, IF_SEL0, IF_SEL1, JSR, LD_ACC,
LD_MREG, LD_PC_NOT, LD_PC_TRK, LD_XREG, LSL, LSR, MFUNC,
MON_CYC_CMPLT, MON_IN_SRVC, MRTI, MSR_CMPLT, MUL, NEG_ADND,
NEG_ONE, NF_SEL0, NF_SEL1, ONE_CYC, OPCOD, OUT_CCR, OUT_MON,
OUT_MREG, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP, RESTOR,
ROL, ROR, RSP, SBC, SBRK, SEC, SEL_BOOL, SEL_DB, SEL_FF_00,
SEL_MEM_A, SEL_MON_ADRS, SEL_STK_PTR, SEL_XREG, SEL_XREG_A,
SEQ_CMPLT, STOP, SUB_ALU, SWI, VECT, WAIT, X_SRC_SEL0,
X_SRC_SEL1, ZERO, ZF_SEL0, ZF_SEL1 );
output ACC_SRC_SEL0, ACC_SRC_SEL1, ADD_1_PC, ADD_ALU, ALU_OP_0, ALU_OP_1,
AND_ALU, BRK_CMPLT;
input BRK_IN_SRVC, BRK_PND, BTB_TST;
input [4:0] CCR;
output CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLC;
input CLK;
output CLR_BT, CLR_DP_H, CLR_DP_L, COM, COMPL_A;
output [7:0] DB_MXD;
output DECODE, DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD, DISCNTY, EN_ACC, EN_BSC,
EN_CF, EN_DP_H, EN_HC, EN_IACK, EN_IF, EN_MREG, EN_NF, EN_STK_PTR,
EN_WR, EN_ZF, EOR;
input FETCH, FRST_WRD;
output HC_SEL0, IF_SEL0, IF_SEL1;
input [7:0] INSTR;
input INT_SEQ, IRQ;
output JSR, LD_ACC, LD_MREG, LD_PC_NOT, LD_PC_TRK, LD_XREG, LSL, LSR, MFUNC;
input MFUNC_REQ;
output MON_CYC_CMPLT, MON_IN_SRVC;
input [7:0] MON_INST;
output MRTI, MSR_CMPLT, MUL;
input MULE;
output NEG_ADND, NEG_ONE, NF_SEL0, NF_SEL1, ONE_CYC;
output [7:0] OPCOD;
output OUT_CCR, OUT_MON, OUT_MREG, OUT_PCH, OUT_PCL, OUT_XREG, PC_XREG, POP;
input RDY, RESET, RESET_DEL;
output RESTOR, ROL, ROR, RSP;
input RST_SEQ;
output SBC, SBRK, SEC, SEL_BOOL, SEL_DB, SEL_FF_00, SEL_MEM_A, SEL_MON_ADRS,
SEL_STK_PTR, SEL_XREG, SEL_XREG_A, SEQ_CMPLT, STOP, SUB_ALU, SWI;
input UPDAT_STAT;
output VECT, WAIT, X_SRC_SEL0, X_SRC_SEL1, ZERO, ZF_SEL0, ZF_SEL1;
wire [9:0] INT_STAT;
wire [9:1] STATE;
wire TAX;
wire CLI;
wire SEI;
wire NOP;
wire TXA;
wire LOI;
wire WORM;
wire MRD;
wire MWR;
wire MRET;
wire INVALID;
wire BTB;
wire BSC;
wire REL;
wire DIR3;
wire INH4;
wire INH5;
wire IX16;
wire IX7;
wire INH8;
wire INH9;
wire IMM;
wire DIRB;
wire EXT;
wire IX2D;
wire IX1E;
wire IXF;
wire NEG;
wire ASR;
wire DEC;
wire INC;
wire TST;
wire CLR;
wire CMP;
wire CPX;
wire AND;
wire BIT;
wire LDA;
wire STA;
wire ADC;
wire ORA;
wire ADD;
wire JMP;
wire LDX;
wire STX;
wire RTI;
wire RTS;
wire SUB;
wire DIS_STATE;
u_seqncr I_1 ( .ACC_SRC_SEL0(ACC_SRC_SEL0), .ACC_SRC_SEL1(ACC_SRC_SEL1),
.ADC(ADC), .ADD(ADD), .ADD_1_PC(ADD_1_PC), .ADD_ALU(ADD_ALU),
.ALU_OP_0(ALU_OP_0), .ALU_OP_1(ALU_OP_1), .AND(AND),
.AND_ALU(AND_ALU), .ASR(ASR), .BIT(BIT), .BRK_PND(BRK_PND),
.BSC(BSC), .BSC_ST2(EN_BSC), .BTB(BTB), .BTB_TST(BTB_TST),
.CCR({ CCR[4:0] }), .CF_SEL0(CF_SEL0), .CF_SEL1(CF_SEL1),
.CF_SEL2(CF_SEL2), .CF_SEL3(CF_SEL3), .CF_SEL4(CF_SEL4),
.CLC(CLC), .CLI(CLI), .CLR(CLR), .CLR_BT(CLR_BT),
.CLR_DP_H(CLR_DP_H), .CLR_DP_L(CLR_DP_L), .CMP(CMP), .COM(COM),
.COMPL_A(COMPL_A), .CPU_CLK(CLK), .CPX(CPX), .DEC(DEC),
.DIR3(DIR3), .DIRB(DIRB), .DIS_FTCH(DIS_FTCH), .DIS_PC(DIS_PC),
.DIS_PC_TRK(DIS_PC_TRK), .DIS_RD(DIS_RD), .DIS_STATE(DIS_STATE),
.DISCNTY(DISCNTY), .EN_ACC(EN_ACC), .EN_CF(EN_CF),
.EN_DP_H(EN_DP_H), .EN_HC(EN_HC), .EN_IACK(EN_IACK),
.EN_IF(EN_IF), .EN_MREG(EN_MREG), .EN_NF(EN_NF),
.EN_STK_PTR(EN_STK_PTR), .EN_WR(EN_WR), .EN_XREG(SEL_XREG),
.EN_ZF(EN_ZF), .EOR(EOR), .EXT(EXT), .IF_SEL0(IF_SEL0),
.IF_SEL1(IF_SEL1), .IMM(IMM), .INC(INC), .INH4(INH4), .INH5(INH5),
.INH8(INH8), .INH9(INH9), .INT_SEQ(INT_SEQ),
.INT_STAT({ INT_STAT[9:0] }), .INVALID(INVALID), .IRQ(IRQ),
.IX16(IX16), .IX1E(IX1E), .IX2D(IX2D), .IX7(IX7), .IXF(IXF),
.JMP(JMP), .JSR(JSR), .LD_ACC(LD_ACC), .LD_MREG(LD_MREG),
.LD_PC_NOT(LD_PC_NOT), .LD_PC_TRK(LD_PC_TRK), .LD_XREG(LD_XREG),
.LDA(LDA), .LDX(LDX), .LOI(LOI), .LSL(LSL), .LSR(LSR),
.MFUNC(MFUNC), .MRD(MRD), .MRET(MRET), .MRTI(MRTI), .MUL(MUL),
.MULE(MULE), .MWR(MWR), .NEG(NEG), .NEG_ADND(NEG_ADND),
.NEG_ONE(NEG_ONE), .NF_SEL0(NF_SEL0), .NF_SEL1(NF_SEL1),
.NOP(NOP), .OPCOD({ OPCOD[3:0] }), .ORA(ORA), .OUT_CCR(OUT_CCR),
.OUT_MON(OUT_MON), .OUT_MREG(OUT_MREG), .OUT_PCH(OUT_PCH),
.OUT_PCL(OUT_PCL), .OUT_XREG(OUT_XREG), .PC_XREG(PC_XREG),
.POP(POP), .REL(REL), .RESET_DEL(RESET_DEL), .RESTOR(RESTOR),
.ROL(ROL), .ROR(ROR), .RSP(RSP), .RST_SEQ(RST_SEQ), .RTI(RTI),
.RTI_STB3(HC_SEL0), .RTS(RTS), .SBC(SBC), .SBRK(SBRK), .SEC(SEC),
.SEI(SEI), .SEL_BOOL(SEL_BOOL), .SEL_DB(SEL_DB),
.SEL_FF_00(SEL_FF_00), .SEL_MEM_A(SEL_MEM_A),
.SEL_MON_ADRS(SEL_MON_ADRS), .SEL_STK_PTR(SEL_STK_PTR),
.SEL_VECT(VECT), .SEL_XREG_A(SEL_XREG_A), .SEQ_CMPLT(SEQ_CMPLT),
.STA(STA), .STATE({ STATE[9:1] }), .STOP(STOP), .STX(STX),
.SUB(SUB), .SUB_ALU(SUB_ALU), .SWI(SWI), .TAX(TAX), .TST(TST),
.TXA(TXA), .WAIT(WAIT), .WORM(WORM), .X_SRC_SEL0(X_SRC_SEL0),
.X_SRC_SEL1(X_SRC_SEL1), .ZERO(ZERO), .ZF_SEL0(ZF_SEL0),
.ZF_SEL1(ZF_SEL1) );
decode I_2 ( .ADC(ADC), .ADD(ADD), .AND(AND), .ASR(ASR), .BIT(BIT),
.BRK_CMPLT(BRK_CMPLT), .BRK_IN_SRVC(BRK_IN_SRVC), .BSC(BSC),
.BTB(BTB), .CLC(CLC), .CLI(CLI), .CLK(CLK), .CLR(CLR), .CMP(CMP),
.COM(COM), .CPX(CPX), .DB_MXD({ DB_MXD[7:0] }), .DEC(DEC),
.DECODE(DECODE), .DIR3(DIR3), .DIRB(DIRB), .DIS_STATE(DIS_STATE),
.EOR(EOR), .EXT(EXT), .FETCH(FETCH), .FRST_WRD(FRST_WRD), .IMM(IMM),
.INC(INC), .INH4(INH4), .INH5(INH5), .INH8(INH8), .INH9(INH9),
.INSTR({ INSTR[7:0] }), .INT_SEQ(INT_SEQ),
.INT_STAT({ INT_STAT[9:0] }), .INVALID(INVALID), .IX16(IX16),
.IX1E(IX1E), .IX2D(IX2D), .IX7(IX7), .IXF(IXF), .JMP(JMP), .JSR(JSR),
.LDA(LDA), .LDX(LDX), .LOI(LOI), .LSL(LSL), .LSR(LSR), .MFUNC(MFUNC),
.MFUNC_REQ(MFUNC_REQ), .MON_CYC_CMPLT(MON_CYC_CMPLT),
.MON_IN_SRVC(MON_IN_SRVC), .MON_INST({ MON_INST[7:0] }), .MRD(MRD),
.MRET(MRET), .MRTI(MRTI), .MSR_CMPLT(MSR_CMPLT), .MUL(MUL),
.MWR(MWR), .NEG(NEG), .NOP(NOP), .ONE_CYC(ONE_CYC),
.OPCOD({ OPCOD[7:0] }), .ORA(ORA), .READY(RDY), .REL(REL),
.RESET(RESET), .ROL(ROL), .ROR(ROR), .RSP(RSP), .RST_SEQ(RST_SEQ),
.RTI(RTI), .RTS(RTS), .SBC(SBC), .SBRK(SBRK), .SEC(SEC), .SEI(SEI),
.SEQ_CMPLT(SEQ_CMPLT), .STA(STA), .STATE({ STATE[9:1] }),
.STOP(STOP), .STX(STX), .SUB(SUB), .SWI(SWI), .TAX(TAX), .TST(TST),
.TXA(TXA), .UDAT_STAT(UPDAT_STAT), .WAIT(WAIT), .WORM(WORM) );
endmodule // ftch_exc
`endif
`ifdef registrs
`else
`define registrs
module registrs( ACC_SRC_SEL0 , ACC_SRC_SEL1, ADD, ALU_OP_0, ALU_OP_1, AND, CF_SEL0,
CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLK, CLR_BT, COMPL_A, DB,
EN_ACC, EN_BSC, EN_CF, EN_HC, EN_IF, EN_MREG, EN_NF, EN_XREG,
EN_ZF, HC_SEL0, IF_SEL0, IF_SEL1, LD_ACC, LD_MREG, LD_XREG,
LSL, LSR, NF_SEL0, NF_SEL1, OPCOD, PROD, READY, RESET, ROL,
ROR, RTB, SBRK, SEL_BOOL, SEL_DB, SEL_FF_00, SEL_MEM_A,
SEL_XREG_A, SUB, SUBC, X_SRC_SEL0, X_SRC_SEL1, XOR, ZF_SEL0,
ZF_SEL1, ACC, BTB_TST, CCR, MREG, XREG );
output [7:0] ACC;
input ACC_SRC_SEL0, ACC_SRC_SEL1, ADD, ALU_OP_0, ALU_OP_1, AND;
output BTB_TST;
output [7:0] CCR;
input CF_SEL0, CF_SEL1, CF_SEL2, CF_SEL3, CF_SEL4, CLK, CLR_BT, COMPL_A;
input [7:0] DB;
input EN_ACC, EN_BSC, EN_CF, EN_HC, EN_IF, EN_MREG, EN_NF, EN_XREG, EN_ZF,
HC_SEL0, IF_SEL0, IF_SEL1, LD_ACC, LD_MREG, LD_XREG, LSL, LSR;
output [7:0] MREG;
input NF_SEL0, NF_SEL1;
input [3:0] OPCOD;
input [15:0] PROD;
input READY, RESET, ROL, ROR, RTB, SBRK, SEL_BOOL, SEL_DB, SEL_FF_00,
SEL_MEM_A, SEL_XREG_A, SUB, SUBC, X_SRC_SEL0, X_SRC_SEL1, XOR;
output [15:0] XREG;
input ZF_SEL0, ZF_SEL1;
wire [7:0] ALU;
wire ADDR_CF;
wire HC;
wire BTB_BIT;
wire MREG_N;
wire MREG_Z;
wire XREG_N;
wire XREG_Z;
wire ACC_N;
wire ACC_Z;
alu I3 ( .ACCUM({ ACC[7:0] }), .ADD(ADD), .ALU({ ALU[7:0] }),
.ALU_OP_0(ALU_OP_0), .ALU_OP_1(ALU_OP_1), .AND(AND), .COMPL_A(COMPL_A),
.COUT_ADDR(ADDR_CF), .CY_FLG(CCR[0]), .DB({ DB[7:0] }), .HC(HC),
.MREG({ MREG[7:0] }), .SEL_BOOL(SEL_BOOL), .SEL_FF_00(SEL_FF_00),
.SEL_MEM_A(SEL_MEM_A), .SEL_XREG_A(SEL_XREG_A), .SUB(SUB), .SUBC(SUBC),
.XOR(XOR), .XREG({ XREG[7:0] }) );
xreg I_1 ( .ACCUM({ ACC[7:0] }), .ALU({ ALU[7:0] }), .CLK(CLK), .CLR(RESET),
.CY_FLG(CCR[0]), .EN_XREG(EN_XREG), .LD_XREG(LD_XREG), .LSL(LSL),
.LSR(LSR), .MULT({ PROD[15:8] }), .N(XREG_N), .OPRND({ DB[7:0] }),
.READY(READY), .ROL(ROL), .ROR(ROR), .X_SRC_SEL0(X_SRC_SEL0),
.X_SRC_SEL1(X_SRC_SEL1), .XREG({ XREG[15:0] }), .Z(XREG_Z) );
mout_reg I_2 ( .ALU({ ALU[7:0] }), .BTB_BIT(BTB_BIT), .BTB_TST(BTB_TST),
.CLK(CLK), .CY_FLG(CCR[0]), .DB({ DB[7:0] }), .EN_BSC(EN_BSC),
.EN_MREG(EN_MREG), .LD_MREG(LD_MREG), .LSL(LSL), .LSR(LSR),
.MOUT_REG({ MREG[7:0] }), .N(MREG_N), .OPCOD({ OPCOD[3:0] }),
.READY(READY), .ROL(ROL), .ROR(ROR), .SEL_DB(SEL_DB), .Z(MREG_Z) );
ccr I_3 ( .AC_D0(ACC[0]), .AC_D7(ACC[7]), .AC_NF(ACC_N), .AC_ZF(ACC_Z),
.ACCUM_HC(HC), .ADDR_CF(ADDR_CF), .BTB_BIT(BTB_BIT),
.CCR({ CCR[7:0] }), .CF_SEL0(CF_SEL0), .CF_SEL1(CF_SEL1),
.CF_SEL2(CF_SEL2), .CF_SEL3(CF_SEL3), .CF_SEL4(CF_SEL4), .CLK(CLK),
.CLR_BT(CLR_BT), .DB_D0(DB[0]), .DB_D1(DB[1]), .DB_D2(DB[2]),
.DB_D3(DB[3]), .DB_D4(DB[4]), .EN_CF(EN_CF), .EN_HC(EN_HC),
.EN_IF(EN_IF), .EN_NF(EN_NF), .EN_ZF(EN_ZF), .HC_SEL0(HC_SEL0),
.IF_SEL0(IF_SEL0), .IF_SEL1(IF_SEL1), .MR_D0(MREG[0]), .MR_D7(MREG[7]),
.MR_NF(MREG_N), .MR_ZF(MREG_Z), .NF_SEL0(NF_SEL0), .NF_SEL1(NF_SEL1),
.READY(READY), .RESET(RESET), .RTB(RTB), .SBRK(SBRK), .XR_D0(XREG[0]),
.XR_D7(XREG[7]), .XR_NF(XREG_N), .XR_ZF(XREG_Z), .ZF_SEL0(ZF_SEL0),
.ZF_SEL1(ZF_SEL1) );
accum I_5 ( .ACCUM({ ACC[7:0] }), .ACUM_SRC_SEL0(ACC_SRC_SEL0),
.ACUM_SRC_SEL1(ACC_SRC_SEL1), .ALU({ ALU[7:0] }), .CLK(CLK),
.CLR(RESET), .CY_FLG(CCR[0]), .EN_ACCUM(EN_ACC), .LD_ACCUM(LD_ACC),
.LSL(LSL), .LSR(LSR), .MULT({ PROD[7:0] }), .N(ACC_N),
.OPRND({ DB[7:0] }), .READY(READY), .ROL(ROL), .ROR(ROR),
.XREG({ XREG[7:0] }), .Z(ACC_Z) );
endmodule // registrs
`endif
`ifdef dout_mux
`else
`define dout_mux
module dout_mux( ACC , CCR, MON_WR_DAT, MREG, OUT_CCR, OUT_MON, OUT_MREG,
OUT_PCTRK_H, OUT_PCTRK_L, OUT_XREG, PC_TRK_H, PC_TRK_L, XREG,
DOUT );
input [7:0] ACC;
input [7:0] CCR;
output [7:0] DOUT;
input [7:0] MON_WR_DAT;
input [7:0] MREG;
input OUT_CCR, OUT_MON, OUT_MREG, OUT_PCTRK_H, OUT_PCTRK_L, OUT_XREG;
input [7:0] PC_TRK_H;
input [7:0] PC_TRK_L;
input [7:0] XREG;
reg [7:0] DOUT;
wire [3:0] MUX_SEL;
assign MUX_SEL = {(OUT_MON | OUT_PCTRK_L), (OUT_PCTRK_H | OUT_MON), (OUT_MON | OUT_MREG | OUT_CCR), (OUT_MON | OUT_MREG | OUT_XREG)};
always @(MUX_SEL or ACC or XREG or CCR or MREG or PC_TRK_H or PC_TRK_L or MON_WR_DAT) begin
casex (MUX_SEL)
4'b0000 : DOUT = ACC;
4'b0001 : DOUT = XREG;
4'b0010 : DOUT = CCR;
4'b0011 : DOUT = MREG;
4'b01xx : DOUT = PC_TRK_H;
4'b10xx : DOUT = PC_TRK_L;
4'b11xx : DOUT = MON_WR_DAT;
default : DOUT = 7'bx;
endcase
end
endmodule // dout_mux
`endif
`ifdef cntl_sig
`else
`define cntl_sig
module cntl_sig( CLK , CLK_LM, DIS_FTCH, DIS_RD, DISCNTY, EN_IACK, EN_WR, ONE_CYC,
READY, RESET, SEQ_CMPLT, STOPD, WAITNG, XCLK_L, DISCNTY_G,
FETCH, FETCH1, FRST_WRD, IACK, IACK1, RD, RDQ1, WR, WR_DEL,
WRQ1 );
input CLK, CLK_LM, DIS_FTCH, DIS_RD, DISCNTY;
output DISCNTY_G;
input EN_IACK, EN_WR;
output FETCH, FETCH1, FRST_WRD, IACK, IACK1;
input ONE_CYC;
output RD, RDQ1;
input READY, RESET, SEQ_CMPLT, STOPD, WAITNG;
output WR, WR_DEL, WRQ1;
input XCLK_L;
reg FETCH1;
reg RDQ1;
reg WRQ1;
reg IACK1;
reg FRST_W;
wire N_17 = RESET;
wire N_18 = READY;
wire N_16 = ~CLK_LM;
wire N_13;
wire RD = N_13 & ~STOPD & ~WAITNG;
always @(posedge CLK or posedge RESET) begin
if (RESET) begin
FETCH1 <= 1'b0;
RDQ1 <= 1'b0;
WRQ1 <= 1'b0;
IACK1 <= 1'b0;
FRST_W <= 1'b0;
end
else begin
if (READY) begin
FETCH1 <= ~DIS_FTCH;
RDQ1 <= ~DIS_RD;
WRQ1 <= EN_WR;
IACK1 <= EN_IACK;
FRST_W <= SEQ_CMPLT & ~ONE_CYC;
end
end
end
half_os I53 ( .CLK(CLK), .CLR(N_17), .D(RDQ1), .E(N_18), .Q(N_13), .XCLK(N_16) );
half_os I_47 ( .CLK(CLK), .CLR(N_17), .D(FETCH1), .E(N_18), .Q(FETCH),
.XCLK(XCLK_L) );
half_os I_48 ( .CLK(CLK_LM), .CLR(N_17), .D(WRQ1), .E(N_18), .Q(WR), .XCLK(N_16) );
half_os I_49 ( .CLK(CLK), .CLR(N_17), .D(WRQ1), .E(N_18), .Q(WR_DEL), .XCLK(N_16) );
half_os I_50 ( .CLK(CLK), .CLR(N_17), .D(IACK1), .E(N_18), .Q(IACK), .XCLK(XCLK_L) );
half_os I_51 ( .CLK(CLK), .CLR(N_17), .D(DISCNTY), .E(N_18), .Q(DISCNTY_G),
.XCLK(XCLK_L) );
half_os I_52 ( .CLK(CLK), .CLR(N_17), .D(FRST_W | ONE_CYC), .E(N_18), .Q(FRST_WRD),
.XCLK(XCLK_L) );
endmodule // cntl_sig
`endif
`ifdef dadrs
`else
`define dadrs
module dadrs( ADD_1_PC , CLK, CLR_DP_HI, CLR_DP_L, DB, EN_DP_HI, EN_STK_PTR, NEG_ADND,
NEG_ONE, PC_TRK, PC_XREG, POP_PUSH, READY, RESET, RSP,
STACK_BASE, XCLK_L, XREG, D_ADR, DP_RAW, STACK );
input ADD_1_PC, CLK, CLR_DP_HI, CLR_DP_L;
output [15:0] D_ADR;
input [7:0] DB;
output [15:0] DP_RAW;
input EN_DP_HI, EN_STK_PTR, NEG_ADND, NEG_ONE;
input [15:0] PC_TRK;
input PC_XREG, POP_PUSH, READY, RESET, RSP;
output [15:0] STACK;
input [15:6] STACK_BASE;
input XCLK_L;
input [15:0] XREG;
wire [15:0] D_ADR;
wire [15:0] X_PC;
assign X_PC = PC_XREG ? PC_TRK : XREG;
assign D_ADR = DP_RAW + X_PC + ADD_1_PC;
dat_ptr I_2 ( .CLK(CLK), .CLR_DP_HI(CLR_DP_HI), .CLR_DP_L(CLR_DP_L),
.DP({ DP_RAW[15:0] }), .EN_DP_HI(EN_DP_HI), .NEG_ADND(NEG_ADND),
.NEG_ONE(NEG_ONE), .OPRND({ DB[7:0] }), .READY(READY) );
stack I_4 ( .CLK(CLK), .EN_STK_PTR(EN_STK_PTR), .POP_PUSH(POP_PUSH),
.READY(READY), .RESET(RESET), .RSP(RSP), .SPQ({ STACK[15:0] }),
.STACK_BASE({ STACK_BASE[15:6] }), .XCLK_L(XCLK_L) );
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