core.v

q6805.zip

`timescale 1ns/1ns  
`define SNH 8'h12 		
`define SNL 8'h77

module core( CLK , CLK_LM, DB, INT, MFUNC_REQ, MON_ADRS, MON_INST, MON_WR_DAT,
             MULE, NMI, PROD, READY, RESET, STACK_BASE, UPDAT_STAT, VECTOR,
             XCLK_L, ACC, BRK_CMPLT, BRK_IN_SRVC, BRK_PND, CCR, CPU_RDY,
             DISCNTY_G, DOUT, FETCH, FETCH1, FRST_WRD, IACK, IACK1, MFUNC,
             MON_CYC_CMPLT, MON_IN_SRVC, MSR_CMPLT, PC, RD, RDQ1, STACK,
             STOPD, WAITNG, WR, WR_DEL, WRQ1, XREG );
 output [7:0] ACC;
output BRK_CMPLT, BRK_IN_SRVC, BRK_PND;
 output [7:0] CCR;
input CLK, CLK_LM;
output CPU_RDY;
 input [7:0] DB;
output DISCNTY_G;
 output [7:0] DOUT;
output FETCH, FETCH1, FRST_WRD, IACK, IACK1;
 input [5:0] INT;
output MFUNC;
input MFUNC_REQ;
 input [15:0] MON_ADRS;
output MON_CYC_CMPLT, MON_IN_SRVC;
 input [7:0] MON_INST;
 input [7:0] MON_WR_DAT;
output MSR_CMPLT;
input MULE, NMI;
 output [15:0] PC;
 input [15:0] PROD;
output RD, RDQ1;
input READY, RESET;
 output [15:0] STACK;
 input [15:6] STACK_BASE;
output STOPD;
input UPDAT_STAT;
 input [15:5] VECTOR;
output WAITNG, WR, WR_DEL, WRQ1;
input XCLK_L;
 output [15:0] XREG;
wire [7:0] MREG;
wire [7:0] DB_MXD;
wire [7:0] OPCOD;
wire COM;
wire MUL;
wire SBRK;
wire JSR;
wire SEC;
wire CLC;
wire BTB_TST;
wire LD_PC_NOT;
wire RESET_DEL;
wire DECODE;
wire OUT_MON;
wire SEL_MON_ADRS;
wire MRTI;
wire OUT_PCH;
wire OUT_PCL;
wire CF_SEL4;
wire CF_SEL3;
wire EOR_ALU;
wire AND_ALU;
wire ADD_ALU;
wire SBC_ALU;
wire SUB_ALU;
wire CLR_DP_L;
wire COMPL_A;
wire ADD_1_PC;
wire NEG_ONE;
wire LD_PC_TRK;
wire IRQ_DET;
wire STOP;
wire WAIT;
wire DISCNTY;
wire RST_SEQ;
wire INT_SEQ;
wire ONE_CYC;
wire EN_ACC;
wire LD_ACC;
wire SEL_DB;
wire ACC_SRC_SEL1;
wire ACC_SRC_SEL0;
wire SEL_XREG;
wire LD_XREG;
wire X_SRC_SEL1;
wire X_SRC_SEL0;
wire EN_CF;
wire CF_SEL2;
wire CF_SEL1;
wire CF_SEL0;
wire EN_BSC;
wire EN_MREG;
wire LD_MREG;
wire RESTOR;
wire EN_HC;
wire VECT;
wire HC_SEL0;
wire EN_IF;
wire IF_SEL1;
wire IF_SEL0;
wire SWI;
wire EN_NF;
wire NF_SEL1;
wire NF_SEL0;
wire EN_ZF;
wire DIS_PC;
wire ZF_SEL1;
wire ZF_SEL0;
wire DIS_PC_TRK;
wire CLR_BT;
wire SEL_STK_PTR;
wire SEL_MEM_A;
wire PC_XREG;
wire SEL_FF_00;
wire NEG_ADND;
wire SEL_XREG_A;
wire CLR_DP_H;
wire EN_DP_H;
wire ALU_OP_1;
wire ALU_OP_0;
wire SEL_BOOL;
wire ZERO;
wire RSP;
wire EN_STK_PTR;
wire POP;
wire DIS_FTCH;
wire DIS_RD;
wire EN_WR;
wire EN_IACK;
wire SEQ_CMPLT;
wire LSR;
wire OUT_MREG;
wire ROR;
wire OUT_CCR;
wire ROL;
wire OUT_XREG;
wire LSL;

out_put I_6 ( .ACC({ ACC[7:0] }), .ADD_1_PC(ADD_1_PC), .BRK_INSRVC(BRK_IN_SRVC),
           .BRK_PND(BRK_PND), .CCR({ CCR[7:0] }), .CLK(CLK), .CLK_LM(CLK_LM),
           .CLR_DP_H(CLR_DP_H), .CLR_DP_L(CLR_DP_L), .DB({ DB[7:0] }),
           .DIS_FTCH(DIS_FTCH), .DIS_PC(DIS_PC), .DIS_PC_TRK(DIS_PC_TRK),
           .DIS_RD(DIS_RD), .DISCNTY(DISCNTY), .DISCNTY_G(DISCNTY_G),
           .DOUT({ DOUT[7:0] }), .EN_DP_H(EN_DP_H), .EN_IACK(EN_IACK),
           .EN_STK_PTR(EN_STK_PTR), .EN_WR(EN_WR), .FETCH(FETCH),
           .FETCH1(FETCH1), .FRST_WRD(FRST_WRD), .IACK(IACK), .IACK1(IACK1),
           .IF(CCR[3]), .INT_SEQ(INT_SEQ), .IRQ({ INT[5:0] }),
           .IRQ_DET(IRQ_DET), .LD_PC_NOT(LD_PC_NOT), .LD_PC_TRK(LD_PC_TRK),
           .MFUNC(MFUNC_REQ), .MON_ADRS({ MON_ADRS[15:0] }),
           .MON_WR_DAT({ MON_WR_DAT[7:0] }), .MREG({ MREG[7:0] }),
           .MRTI(MRTI), .MUL(MUL), .MULE(MULE), .NEG_ADND(NEG_ADND),
           .NEG_ONE(NEG_ONE), .NMI(NMI), .ONE_CYC(ONE_CYC), .OUT_CCR(OUT_CCR),
           .OUT_MON(OUT_MON), .OUT_MREG(OUT_MREG), .OUT_PCTRK_H(OUT_PCH),
           .OUT_PCTRK_L(OUT_PCL), .OUT_XREG(OUT_XREG), .PC({ PC[15:0] }),
           .PC_XREG(PC_XREG), .POP(POP), .RD(RD), .RDQ1(RDQ1), .READY(CPU_RDY),
           .RESET(RESET), .RESET_DEL(RESET_DEL), .RESET_SEQ(RST_SEQ),
           .RESTOR(RESTOR), .RSP(RSP), .SBRK(SBRK),
           .SEL_MON_ADRS(SEL_MON_ADRS), .SEL_STK_PTR(SEL_STK_PTR),
           .SEL_VECT(VECT), .SEQ_CMPLT(SEQ_CMPLT), .STACK({ STACK[15:0] }),
           .STACK_BASE({ STACK_BASE[15:6] }), .STOPD(STOPD), .SWI(SWI),
           .VECTOR({ VECTOR[15:5] }), .WAITNG(WAITNG), .WR(WR),
           .WR_DEL(WR_DEL), .WRQ1(WRQ1), .XCLK_L(XCLK_L),
           .XREG({ XREG[15:0] }), .ZERO(ZERO) );
wait_stp I_5 ( .CLK(CLK), .CLR_WT_STP(IRQ_DET), .CPU_RDY(CPU_RDY),
            .MFUNC_REQ(MFUNC_REQ), .READY_IN(READY), .RESET(RESET),
            .STOP(STOP), .STOPD(STOPD), .WAIT(WAIT), .WAITNG(WAITNG) );
ftch_exc I_1 ( .ACC_SRC_SEL0(ACC_SRC_SEL0), .ACC_SRC_SEL1(ACC_SRC_SEL1),
            .ADD_1_PC(ADD_1_PC), .ADD_ALU(ADD_ALU), .ALU_OP_0(ALU_OP_0),
            .ALU_OP_1(ALU_OP_1), .AND_ALU(AND_ALU), .BRK_CMPLT(BRK_CMPLT),
            .BRK_IN_SRVC(BRK_IN_SRVC), .BRK_PND(BRK_PND), .BTB_TST(BTB_TST),
            .CCR({ CCR[4:0] }), .CF_SEL0(CF_SEL0), .CF_SEL1(CF_SEL1),
            .CF_SEL2(CF_SEL2), .CF_SEL3(CF_SEL3), .CF_SEL4(CF_SEL4),
            .CLC(CLC), .CLK(CLK), .CLR_BT(CLR_BT), .CLR_DP_H(CLR_DP_H),
            .CLR_DP_L(CLR_DP_L), .COM(COM), .COMPL_A(COMPL_A),
            .DB_MXD({ DB_MXD[7:0] }), .DECODE(DECODE), .DIS_FTCH(DIS_FTCH),
            .DIS_PC(DIS_PC), .DIS_PC_TRK(DIS_PC_TRK), .DIS_RD(DIS_RD),
            .DISCNTY(DISCNTY), .EN_ACC(EN_ACC), .EN_BSC(EN_BSC),
            .EN_CF(EN_CF), .EN_DP_H(EN_DP_H), .EN_HC(EN_HC),
            .EN_IACK(EN_IACK), .EN_IF(EN_IF), .EN_MREG(EN_MREG),
            .EN_NF(EN_NF), .EN_STK_PTR(EN_STK_PTR), .EN_WR(EN_WR),
            .EN_ZF(EN_ZF), .EOR(EOR_ALU), .FETCH(FETCH), .FRST_WRD(FRST_WRD),
            .HC_SEL0(HC_SEL0), .IF_SEL0(IF_SEL0), .IF_SEL1(IF_SEL1),
            .INSTR({ DB[7:0] }), .INT_SEQ(INT_SEQ), .IRQ(IRQ_DET), .JSR(JSR),
            .LD_ACC(LD_ACC), .LD_MREG(LD_MREG), .LD_PC_NOT(LD_PC_NOT),
            .LD_PC_TRK(LD_PC_TRK), .LD_XREG(LD_XREG), .LSL(LSL), .LSR(LSR),
            .MFUNC(MFUNC), .MFUNC_REQ(MFUNC_REQ),
            .MON_CYC_CMPLT(MON_CYC_CMPLT), .MON_IN_SRVC(MON_IN_SRVC),
            .MON_INST({ MON_INST[7:0] }), .MRTI(MRTI), .MSR_CMPLT(MSR_CMPLT),
            .MUL(MUL), .MULE(MULE), .NEG_ADND(NEG_ADND), .NEG_ONE(NEG_ONE),
            .NF_SEL0(NF_SEL0), .NF_SEL1(NF_SEL1), .ONE_CYC(ONE_CYC),
            .OPCOD({ OPCOD[7:0] }), .OUT_CCR(OUT_CCR), .OUT_MON(OUT_MON),
            .OUT_MREG(OUT_MREG), .OUT_PCH(OUT_PCH), .OUT_PCL(OUT_PCL),
            .OUT_XREG(OUT_XREG), .PC_XREG(PC_XREG), .POP(POP), .RDY(CPU_RDY),
            .RESET(RESET), .RESET_DEL(RESET_DEL), .RESTOR(RESTOR), .ROL(ROL),
            .ROR(ROR), .RSP(RSP), .RST_SEQ(RST_SEQ), .SBC(SBC_ALU),
            .SBRK(SBRK), .SEC(SEC), .SEL_BOOL(SEL_BOOL), .SEL_DB(SEL_DB),
            .SEL_FF_00(SEL_FF_00), .SEL_MEM_A(SEL_MEM_A),
            .SEL_MON_ADRS(SEL_MON_ADRS), .SEL_STK_PTR(SEL_STK_PTR),
            .SEL_XREG(SEL_XREG), .SEL_XREG_A(SEL_XREG_A),
            .SEQ_CMPLT(SEQ_CMPLT), .STOP(STOP), .SUB_ALU(SUB_ALU), .SWI(SWI),
            .UPDAT_STAT(UPDAT_STAT), .VECT(VECT), .WAIT(WAIT),
            .X_SRC_SEL0(X_SRC_SEL0), .X_SRC_SEL1(X_SRC_SEL1), .ZERO(ZERO),
            .ZF_SEL0(ZF_SEL0), .ZF_SEL1(ZF_SEL1) );
registrs I_3 ( .ACC({ ACC[7:0] }), .ACC_SRC_SEL0(ACC_SRC_SEL0),
            .ACC_SRC_SEL1(ACC_SRC_SEL1), .ADD(ADD_ALU), .ALU_OP_0(ALU_OP_0),
            .ALU_OP_1(ALU_OP_1), .AND(AND_ALU), .BTB_TST(BTB_TST),
            .CCR({ CCR[7:0] }), .CF_SEL0(CF_SEL0), .CF_SEL1(CF_SEL1),
            .CF_SEL2(CF_SEL2), .CF_SEL3(CF_SEL3), .CF_SEL4(CF_SEL4),
            .CLK(CLK), .CLR_BT(CLR_BT), .COMPL_A(COMPL_A), .DB({ DB[7:0] }),
            .EN_ACC(EN_ACC), .EN_BSC(EN_BSC), .EN_CF(EN_CF), .EN_HC(EN_HC),
            .EN_IF(EN_IF), .EN_MREG(EN_MREG), .EN_NF(EN_NF),
            .EN_XREG(SEL_XREG), .EN_ZF(EN_ZF), .HC_SEL0(HC_SEL0),
            .IF_SEL0(IF_SEL0), .IF_SEL1(IF_SEL1), .LD_ACC(LD_ACC),
            .LD_MREG(LD_MREG), .LD_XREG(LD_XREG), .LSL(LSL), .LSR(LSR),
            .MREG({ MREG[7:0] }), .NF_SEL0(NF_SEL0), .NF_SEL1(NF_SEL1),
            .OPCOD({ OPCOD[3:0] }), .PROD({ PROD[15:0] }), .READY(CPU_RDY),
            .RESET(RESET), .ROL(ROL), .ROR(ROR), .RTB(MRTI), .SBRK(SBRK),
            .SEL_BOOL(SEL_BOOL), .SEL_DB(SEL_DB), .SEL_FF_00(SEL_FF_00),
            .SEL_MEM_A(SEL_MEM_A), .SEL_XREG_A(SEL_XREG_A), .SUB(SUB_ALU),
            .SUBC(SBC_ALU), .X_SRC_SEL0(X_SRC_SEL0), .X_SRC_SEL1(X_SRC_SEL1),
            .XOR(EOR_ALU), .XREG({ XREG[15:0] }), .ZF_SEL0(ZF_SEL0),
            .ZF_SEL1(ZF_SEL1) );

endmodule // core


`ifdef out_put
`else
`define out_put
module out_put( ACC , ADD_1_PC, CCR, CLK, CLK_LM, CLR_DP_H, CLR_DP_L, DB,
                DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD, DISCNTY, EN_DP_H,
                EN_IACK, EN_STK_PTR, EN_WR, IF, IRQ, LD_PC_NOT, LD_PC_TRK,
                MFUNC, MON_ADRS, MON_WR_DAT, MREG, MRTI, MUL, MULE, NEG_ADND,
                NEG_ONE, NMI, ONE_CYC, OUT_CCR, OUT_MON, OUT_MREG,
                OUT_PCTRK_H, OUT_PCTRK_L, OUT_XREG, PC_XREG, POP, READY,
                RESET, RESTOR, RSP, SBRK, SEL_MON_ADRS, SEL_STK_PTR, SEL_VECT,
                SEQ_CMPLT, STACK_BASE, STOPD, SWI, VECTOR, WAITNG, XCLK_L,
                XREG, ZERO, BRK_INSRVC, BRK_PND, DISCNTY_G, DOUT, FETCH,
                FETCH1, FRST_WRD, IACK, IACK1, INT_SEQ, IRQ_DET, PC, RD, RDQ1,
                RESET_DEL, RESET_SEQ, STACK, WR, WR_DEL, WRQ1 );
 input [7:0] ACC;
input ADD_1_PC;
output BRK_INSRVC, BRK_PND;
 input [7:0] CCR;
input CLK, CLK_LM, CLR_DP_H, CLR_DP_L;
 input [7:0] DB;
input DIS_FTCH, DIS_PC, DIS_PC_TRK, DIS_RD, DISCNTY;
output DISCNTY_G;
 output [7:0] DOUT;
input EN_DP_H, EN_IACK, EN_STK_PTR, EN_WR;
output FETCH, FETCH1, FRST_WRD, IACK, IACK1;
input IF;
output INT_SEQ;
 input [5:0] IRQ;
output IRQ_DET;
input LD_PC_NOT, LD_PC_TRK, MFUNC;
 input [15:0] MON_ADRS;
 input [7:0] MON_WR_DAT;
 input [7:0] MREG;
input MRTI, MUL, MULE, NEG_ADND, NEG_ONE, NMI, ONE_CYC, OUT_CCR, OUT_MON,
OUT_MREG, OUT_PCTRK_H, OUT_PCTRK_L, OUT_XREG;
 output [15:0] PC;
input PC_XREG, POP;
output RD, RDQ1;
input READY, RESET;
output RESET_DEL, RESET_SEQ;
input RESTOR, RSP, SBRK, SEL_MON_ADRS, SEL_STK_PTR, SEL_VECT, SEQ_CMPLT;
 output [15:0] STACK;
 input [15:6] STACK_BASE;
input STOPD, SWI;
 input [15:5] VECTOR;
input WAITNG;
output WR, WR_DEL, WRQ1;
input XCLK_L;
 input [15:0] XREG;
input ZERO;
wire [15:0] DP_RAW;
wire [15:0] PC_TRK;
wire [15:0] DP;
wire N_1;
wire RESETB;
wire READYB;



assign FRST_WRD = ~INT_SEQ & N_1;

assign RESETB = RESET;

assign READYB = READY;

dout_mux I_1 ( .ACC({ ACC[7:0] }), .CCR({ CCR[7:0] }), .DOUT({ DOUT[7:0] }),
            .MON_WR_DAT({ MON_WR_DAT[7:0] }), .MREG({ MREG[7:0] }),
            .OUT_CCR(OUT_CCR), .OUT_MON(OUT_MON), .OUT_MREG(OUT_MREG),
            .OUT_PCTRK_H(OUT_PCTRK_H), .OUT_PCTRK_L(OUT_PCTRK_L),
            .OUT_XREG(OUT_XREG), .PC_TRK_H({ PC_TRK[15:8] }),
            .PC_TRK_L({ PC_TRK[7:0] }), .XREG({ XREG[7:0] }) );
cntl_sig I_2 ( .CLK(CLK), .CLK_LM(CLK_LM), .DIS_FTCH(DIS_FTCH), .DIS_RD(DIS_RD),
            .DISCNTY(DISCNTY), .DISCNTY_G(DISCNTY_G), .EN_IACK(EN_IACK),
            .EN_WR(EN_WR), .FETCH(FETCH), .FETCH1(FETCH1), .FRST_WRD(N_1),
            .IACK(IACK), .IACK1(IACK1), .ONE_CYC(ONE_CYC), .RD(RD),
            .RDQ1(RDQ1), .READY(READYB), .RESET(RESETB),
            .SEQ_CMPLT(SEQ_CMPLT), .STOPD(STOPD), .WAITNG(WAITNG), .WR(WR),
            .WR_DEL(WR_DEL), .WRQ1(WRQ1), .XCLK_L(XCLK_L) );
dadrs I_3 ( .ADD_1_PC(ADD_1_PC), .CLK(CLK), .CLR_DP_HI(CLR_DP_H),
         .CLR_DP_L(CLR_DP_L), .D_ADR({ DP[15:0] }), .DB({ DB[7:0] }),
         .DP_RAW({ DP_RAW[15:0] }), .EN_DP_HI(EN_DP_H),
         .EN_STK_PTR(EN_STK_PTR), .NEG_ADND(NEG_ADND), .NEG_ONE(NEG_ONE),
         .PC_TRK({ PC_TRK[15:0] }), .PC_XREG(PC_XREG), .POP_PUSH(POP),
         .READY(READYB), .RESET(RESETB), .RSP(RSP), .STACK({ STACK[15:0] }),
         .STACK_BASE({ STACK_BASE[15:6] }), .XCLK_L(XCLK_L),
         .XREG({ XREG[15:0] }) );
pc I_4 ( .BRK_INSRVC(BRK_INSRVC), .BRK_PND(BRK_PND), .CLK(CLK), .DIS_PC(DIS_PC),
      .DIS_PC_TRK(DIS_PC_TRK), .DP({ DP[15:0] }), .DP_RAW({ DP_RAW[15:0] }),
      .EN_IACK(EN_IACK), .FRST_WRD(FRST_WRD), .IF(IF), .INT_SEQ(INT_SEQ),
      .IRQ({ IRQ[5:0] }), .IRQ_DET(IRQ_DET), .LD_PC_NOT(LD_PC_NOT),
      .LD_PC_TRK(LD_PC_TRK), .MFUNC(MFUNC), .MON_ADRS({ MON_ADRS[15:0] }),
      .MRTI(MRTI), .MUL(MUL), .MULE(MULE), .NMI(NMI), .PC({ PC[15:0] }),
      .PC_DLY({ PC_TRK[15:0] }), .READY(READYB), .RESET(RESETB),
      .RESET_DEL(RESET_DEL), .RESET_SEQ(RESET_SEQ), .RESTOR(RESTOR),
      .SBRK(SBRK), .SEL_DPZERO(ZERO), .SEL_MON_ADRS(SEL_MON_ADRS),
      .SEL_STK(SEL_STK_PTR), .SEL_VECT(SEL_VECT), .SEQ_CMPLT(SEQ_CMPLT),
      .STAK({ STACK[15:0] }), .SWI(SWI), .VECTOR({ VECTOR[15:5] }),
      .XCLK_L(XCLK_L) );

endmodule // out_put

`endif

`ifdef wait_stp
`else
`define wait_stp
module wait_stp( CLK , CLR_WT_STP, MFUNC_REQ, READY_IN, RESET, STOP, WAIT,
                 CPU_RDY, STOPD, WAITNG );
input CLK, CLR_WT_STP;
output CPU_RDY;
input MFUNC_REQ, READY_IN, RESET, STOP;
output STOPD;
input WAIT;
output WAITNG;


reg	 WAITNG;
reg	 STOPD;
reg	 WAIT_STP_DEL;

wire CPU_RDY;

wire CLR_STOPD = RESET | CLR_WT_STP | MFUNC_REQ;
wire EN_WAITING =  (CLR_WT_STP | MFUNC_REQ) ? ~WAITNG : 1'b1;
wire EN_STOPD = (CLR_WT_STP | MFUNC_REQ) ? ~STOPD : 1'b1;

assign CPU_RDY = READY_IN & ~WAITNG & ~STOPD & ~ WAIT_STP_DEL;


always @(posedge CLK or posedge RESET) begin
	if (RESET) begin
		WAITNG <= 1'b0;
	end
	else begin
		if (EN_WAITING) WAITNG <= WAIT & ~(CLR_WT_STP | MFUNC_REQ);
	end
end

always @(posedge CLK or posedge CLR_STOPD) begin
	if (CLR_STOPD) begin
		STOPD <= 1'b0;
	end
	else begin
		if (EN_STOPD) STOPD <= STOP & ~(CLR_WT_STP | MFUNC_REQ);
	end
end

always @(posedge CLK) begin
	WAIT_STP_DEL <= WAITNG | STOPD;
end


endmodule // wait_stp

`endif

`ifdef ftch_exc
`else
`define ftch_exc
module ftch_exc( BRK_IN_SRVC , BRK_PND, BTB_TST, CCR, CLK, FETCH, FRST_WRD, INSTR,
                 INT_SEQ, IRQ, MFUNC_REQ, MON_INST, MULE, RDY, RESET,
                 RESET_DEL, RST_SEQ, UPDAT_STAT, ACC_SRC_SEL0, ACC_SRC_SEL1,