ncxscale.h

CE下 NET2778 NDIS Drivers, 在每个平台上都可以使用

#ifndef NCXSCALE_H
#define NCXSCALE_H
///////////////////////////////////////////////////////////////////////////////
// XSCALE Specifics  Probably should be moved somewhere else
#define DMA_MAP_VALID_MASK  (0x1U << 7)  // Request is mapped to a valid channel indicated by DRCMRx(3:0)

#define DCSR_RUN            (0x1U << 31) // run, 1=start
#define DCSR_NOFETCH        (0x1U << 30) // Descriptor fetch mode, 0 = fetch
#define DCSR_BUSERRINTR     (0x1U << 0)  // Bus error status bit
#define DCSR_STARTINTR      (0x1U << 1)  // Descriptor fetch status 
#define DCSR_ENDINTR        (0x1U << 2)  // finish status
#define DCSR_STOPINTR       (0x1U << 3)  // stopped status
#define DCSR_REQPEND        (0x1U << 8)  // Request Pending (read-only)
#define DCSR_STARTIRQEN     (0x1U << 21) // Enable the start interrupt (when the descriptor is loaded)
#define DCSR_STOPIRQEN       (0x1U << 29) // Enable the stopped interrupt (when the descriptor is done)

#define DDADR_STOPCONTINUE  (0x1U << 0)

typedef struct  
{
    unsigned len         :13;
    unsigned rsv0         :1;   
    unsigned width         :2; 
    unsigned size         :2;
    unsigned endian         :1;
    unsigned flybyt          :1;
    unsigned flybys          :1;
    unsigned endirqen    :1;
    unsigned startirqen  :1;
    unsigned rsv1        :5;
    unsigned flowtrg     :1;
    unsigned flowsrc     :1;
    unsigned inctrgadd   :1;
    unsigned incsrcadd   :1;
} DCMD_REGBITS;

typedef union DMA_CMDREG_t // allow bitfields or masks
{
    volatile DCMD_REGBITS   DcmdReg;
    volatile DWORD          DcmdDword;
} DMA_CMDREG;

#define RBUFF            15    
#define RRR                12    // ROM/SRAM recovery time = RRR*2 memclks
#define RDN                8    // ROM delay next access = RDN + 2 (For VLIO, RDF must >= 2)
#define RDF                4    // ROM delay first access = RDF + 1 memclks (in VLIO RDF must be >=3)

#define RBW                3    // ROM bus width, 0 = 32 bit, 1 = 16 bit
#define        RBW_32BITS        0
#define        RBW_16BITS        1

#define    RT                0    // ROM type
#define        NON_BURST_ROM_OR_FLASH        0
#define        SRAM                        1
#define        BURST_OF_FOUR_ROM_OR_FLASH    2
#define        BURST_OF_EIGHT_ROM_OR_FLASH    3
#define        VLIO                        4

#define        K0DB2                        14

#define GPIO_NET2272_INT    GPIO_9

#endif // NCXSCALE_H