📄 net2272.h
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/******************************************************************************
Copyright (C) 2003, 2004, NetChip Technology, Inc. (http://www.netchip.com)
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND,
EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A PARTICULAR PURPOSE.
NET2272.H
NetChip NET2272 constants - header file
These NET2272 register and bit field definitions are extracted
from the NET2272 specification.
******************************************************************************/
///////////////////////////////////////////////////////////////////////////////
#ifndef NET2272_H
#define NET2272_H
///////////////////////////////////////////////////////////////////////////////
// NET2272 register and bit field definitions
// - Definitions extracted from NET2272 chip specification
// - Masks for bit fields are not defined. Use the shift operator ('<<')
// to build masks where needed in your code:
// if (ChipReg & (1<<BIT_FIELD_NAME)) {DoSomething();}
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
// Main Control Registers
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
#define REGADDRPTR 0x00
///////////////////////////////////////////////////////////////////////////////
#define REGDATA 0x01
///////////////////////////////////////////////////////////////////////////////
#define IRQSTAT0 0x02
// Interrupt Status Register (low byte)
#define ENDPOINT_0_INTERRUPT 0 //
#define ENDPOINT_A_INTERRUPT 1 //
#define ENDPOINT_B_INTERRUPT 2 //
#define ENDPOINT_C_INTERRUPT 3 //
#define VIRTUALIZED_ENDPOINT_INTERRUPT 4 //
#define SETUP_PACKET_INTERRUPT 5 //
#define DMA_DONE_INTERRUPT 6 //
#define SOF_INTERRUPT 7 //
///////////////////////////////////////////////////////////////////////////////
#define IRQSTAT1 0x03
// Interrupt Status Register (high byte)
#define CONTROL_STATUS_INTERRUPT 1 //
#define VBUS_INTERRUPT 2 //
#define SUSPEND_REQUEST_INTERRUPT 3 //
#define SUSPEND_REQUEST_CHANGE_INTERRUPT 4 //
#define RESUME_INTERRUPT 5 // Chip has resumed
#define ROOT_PORT_RESET_INTERRUPT 6 //
#define RESET_STATUS 7 // Self clearing
///////////////////////////////////////////////////////////////////////////////
#define PAGESEL 0x04
///////////////////////////////////////////////////////////////////////////////
#define DMAREQ 0x1c
// DMA Request Control Register
#define DMA_ENDPOINT_SELECT 0 // DMA Endpoint Select: 0:EPA, 1:EPB
#define DREQ_POLARITY 1 // 0:DREQ pin is active low, 1:DREQ pin is active high
#define DACK_POLARITY 2 // 0:DACK pin is active low, 1:DACK pin is active high
#define EOT_POLARITY 3 // 0:EOT pin is active low, 1:EOT pin is active high
#define DMA_CONTROL_DACK 4 // 0:Use only DACK, 1:use RD#, WR# and DACK
#define DMA_REQUEST_ENABLE 5 // Start DMA cycles
#define DMA_REQUEST 6 // Reflects the state of the DREQ pin
#define DMA_BUFFER_VALID 7 //
///////////////////////////////////////////////////////////////////////////////
#define SCRATCH 0x1d
///////////////////////////////////////////////////////////////////////////////
#define IRQENB0 0x20
// Interrupt Enable Register (low byte)
#define ENDPOINT_0_INTERRUPT_ENABLE 0 //
#define ENDPOINT_A_INTERRUPT_ENABLE 1 //
#define ENDPOINT_B_INTERRUPT_ENABLE 2 //
#define ENDPOINT_C_INTERRUPT_ENABLE 3 //
#define VIRTUALIZED_ENDPOINT_INTERRUPT_ENABLE 4 //
#define SETUP_PACKET_INTERRUPT_ENABLE 5 //
#define DMA_DONE_INTERRUPT_ENABLE 6 //
#define SOF_INTERRUPT_ENABLE 7 //
///////////////////////////////////////////////////////////////////////////////
#define IRQENB1 0x21
// Interrupt Enable Register (high byte)
#define CONTROL_STATUS_INTERRUPT_ENABLE 1 //
#define VBUS_INTERRUPT_ENABLE 2 //
#define SUSPEND_REQUEST_INTERRUPT_ENABLE 3 //
#define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 4 //
#define RESUME_INTERRUPT_ENABLE 5 //
#define ROOT_PORT_RESET_INTERRUPT_ENABLE 6 //
///////////////////////////////////////////////////////////////////////////////
#define LOCCTL 0x22
// Local Bus Control Register
#define DATA_WIDTH 0 // EP Data bus width: Clear:8-bit Set:16 bit (Default: 8-bit)
#define LOCAL_CLOCK_OUTPUT 1 //
#define DMA_SPLIT_BUS_MODE 4 //
#define BYTE_SWAP 5 //
#define BUFFER_CONFIGURATION 6 //
// Local Clock Output (bits 3:1 in LOCCTL register)
#define LOCAL_CLOCK_OUTPUT_OFF 0 // No output
#define LOCAL_CLOCK_OUTPUT_3_75MHZ 1 //
#define LOCAL_CLOCK_OUTPUT_7_5MHZ 2 // (Default)
#define LOCAL_CLOCK_OUTPUT_15MHZ 3 //
#define LOCAL_CLOCK_OUTPUT_30MHZ 4 //
#define LOCAL_CLOCK_OUTPUT_60MHZ 5 //
// Buffer Configuration (bits 7:6 in LOCCTL register)
#define BUFFER_CONFIGURATION_EPA512_EPB512 0 // EPA and EPB double buffered (default)
#define BUFFER_CONFIGURATION_EPA1024_EPB512 1 // EPB double buffered
#define BUFFER_CONFIGURATION_EPA1024_EPB1024 2 // EPA and EPB not double buffered
#define BUFFER_CONFIGURATION_EPA1024DB 3 // EPA double buffered (EPB disabled)
///////////////////////////////////////////////////////////////////////////////
// Address of "NET2270-compatible" silicon revision register
// - The NET2272 has two chip revision registers. This revision register
// is compatible with the NET2270. For a NET2272, this register should
// always read a value of 0x40. (The CHIPREV_2272 register contains the
// value of the NET2272 silicon revision.)
#define CHIPREV_LEGACY 0x23
///////////////////////////////////////////////////////////////////////////////
// The NET2272 has two chip revision registers:
// The NET2272 'legacy' revision register is in the same location
// as the NET2270 CHIP_REV register (address 0x23). The value in the legacy
// revision register of a NET2272, regardless of the NET2272 silicon revision,
// is always 0x40.
// - The NET2272's actual silicon revision can be found in register CHIPREV_2272.
// - Tip: NET2270 firmware can be applied to the NET2272 with only minor modifications
#define NET2270_LEGACY_REV 0x40
///////////////////////////////////////////////////////////////////////////////
#define LOCCTL1 0x24
// Local Bus Control Register 1
#define DMA_MODE 0
#define DMA_DACK_ENABLE 2
// DMA MODE
#define SLOW_DREQ 0 //
#define FAST_DREQ 1 //
#define BURST_MODE 2
///////////////////////////////////////////////////////////////////////////////
#define CHIPREV_2272 0x25
// Chip revision values found in CHIPREV_2272
// - All released values for CHIPREV_2272:
#define CHIPREV_NET2272_R1 0x10 // "NET2272 Rev 1"
#define CHIPREV_NET2272_R1A 0x11 // "NET2272 Rev 1A
///////////////////////////////////////////////////////////////////////////////
// USB Control Registers
///////////////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////////////
#define USBCTL0 0x18
// USB Control Register (low byte)
#define IO_WAKEUP_ENABLE 1 //
#define USB_DETECT_ENABLE 3 //
#define USB_ROOT_PORT_WAKEUP_ENABLE 5 //
///////////////////////////////////////////////////////////////////////////////
#define USBCTL1 0x19
// USB Control Register (low byte)
#define VBUS_PIN 0 //
#define USB_FULL_SPEED 1 //
#define USB_HIGH_SPEED 2 //
#define GENERATE_RESUME 3 //
#define VIRTUAL_ENDPOINT_ENABLE 4 //
///////////////////////////////////////////////////////////////////////////////
#define FRAME0 0x1a
///////////////////////////////////////////////////////////////////////////////
#define FRAME1 0x1b
///////////////////////////////////////////////////////////////////////////////
#define OURADDR 0x30
// Force USB Address update immediately (bit 7 in OURADDR register)
#define FORCE_IMMEDIATE 7 //
///////////////////////////////////////////////////////////////////////////////
#define USBDIAG 0x31
// USB Diagnostic Register
#define FORCE_TRANSMIT_CRC_ERROR 0 //
#define PREVENT_TRANSMIT_BIT_STUFF 1 //
#define FORCE_RECEIVE_ERROR 2 //
#define FAST_TIMES 4 //
///////////////////////////////////////////////////////////////////////////////
#define USBTEST 0x32
// USB Test Modes
#define TEST_MODE_SELECT 0 // Bits 2:0
// USB Test Mode selectors (See TEST_MODE_SELECT in USBTEST)
// - NET2272 Test Mode Select maps directly to USB Test Mode Selectors (USB 2.0, Table 9-7)
#define NORMAL_OPERATION 0 //
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