plx.h

CE下 NET2778 NDIS Drivers, 在每个平台上都可以使用

///////////////////////////////////////////////////////////////////////////////
// PLX9054 registers
//  - Limited to the registers we use
///////////////////////////////////////////////////////////////////////////////
#define INTCSR      0x68
// INTCSR bits
#define     PCI_INTERRUPT_ENABLE                8
#define     LOCAL_INTERRUPT_INPUT_ENABLE        11
#define     LOCAL_INPUT_INTERRUPT_ACTIVE        15
#define     LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE 18
#define     LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE 19
#define     DMA_CHANNEL_0_INTERRUPT_ACTIVE      21
#define     DMA_CHANNEL_1_INTERRUPT_ACTIVE      22

///////////////////////////////////////////////////////////////////////////////
#define CNTRL       0x6C
// CNTRL bits
#define     RELOAD_CONFIGURATION_REGISTERS      29
#define     PCI_ADAPTER_SOFTWARE_RESET          30

///////////////////////////////////////////////////////////////////////////////
// Special OR'ing of INTCSR bits 
#define LOCAL_INTERRUPT_TEST ((1<<LOCAL_INPUT_INTERRUPT_ACTIVE)|(1<<LOCAL_INTERRUPT_INPUT_ENABLE))
#define DMA_CHANNEL_0_TEST ((1<<DMA_CHANNEL_0_INTERRUPT_ACTIVE)|(1<<LOCAL_DMA_CHANNEL_0_INTERRUPT_ENABLE))
#define DMA_CHANNEL_1_TEST ((1<<DMA_CHANNEL_1_INTERRUPT_ACTIVE)|(1<<LOCAL_DMA_CHANNEL_1_INTERRUPT_ENABLE))

///////////////////////////////////////////////////////////////////////////////
#define DMAMODE0    0x80
// DMAMODE bits (Applies to both DMAMODE0 and DMAMODE1)
#define     LOCAL_BUS_WIDTH                     0
#define     INTERNAL_WAIT_STATES                2
#define     TA_READY_INPUT_ENABLE               6   // TA#/READY# Input Enable (TRUE after reset) (This label doesn't translate to C very well!)
#define     LOCAL_BURST_ENABLE                  8
#define     SCATTER_GATHER_MODE                 9
#define     DONE_INTERRUPT_ENABLE               10
#define     LOCAL_ADDRESSING_MODE               11  // PLX9054: "Writing a one holds the Local Address constant."
#define     DEMAND_MODE                         12
#define     DMA_EOT_ENABLE                      14
#define     FAST_SLOW_TERMINATE_MODE_SELECT     15
#define     DMA_CHANNEL_INTERRUPT_SELECT        17  // PLX9054: "Writing a one routes DMA interrupt to the PCI Bus interrupt."

///////////////////////////////////////////////////////////////////////////////
#define DMAPADR0    0x84

///////////////////////////////////////////////////////////////////////////////
#define DMALADR0    0x88

///////////////////////////////////////////////////////////////////////////////
#define DMASIZ0     0x8c

///////////////////////////////////////////////////////////////////////////////
#define DMADPR0     0x90
// DMADPR bits (Applies to both DMADPR0 and DMADPR1)
#define     DESCRIPTOR_LOCATION                 0
#define     END_OF_CHAIN                        1
#define     INTERRUPT_AFTER_TERMINAL_COUNT      2
#define     DIRECTION_OF_TRANSFER               3   // 1:Local to PCI; 0:PCI to Local

///////////////////////////////////////////////////////////////////////////////
// Note: DMACSR0 is a BYTE, not a DWORD!
#define DMACSR0     0xa8
// DMACSR bits (Applies to both DMACSR0 and DMACSR1)
#define     CHANNEL_ENABLE                      0
#define     CHANNEL_START                       1
#define     CHANNEL_ABORT                       2
#define     CHANNEL_CLEAR_INTERRUPT             3
#define     CHANNEL_DONE                        4

///////////////////////////////////////////////////////////////////////////////
#define LBRD1       0xf8
// LBRD1 bits (Applies to both LBRD0 and LBRD1)
#define     MEMORY_SPACE_LOCAL_BUS_WIDTH        0
#define	    W8_BIT					0
#define     W16_BIT					1