verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 19 行

// generated by newgenasym  Fri Oct 24 14:59:30 2008


module opampadj (m, n1, n2, out, p, vm, vp);
    input m;
    output n1;
    input n2;
    output out;
    input p;
    input vm;
    input vp;


    initial
        begin
        end

endmodule