verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 20 行

// generated by newgenasym  Fri Oct 24 14:14:46 2008


module dg419 (gnd, ina1, ina2, ind, out, van, vap, vd);
    input gnd;
    input ina1;
    input ina2;
    input ind;
    input out;
    input van;
    input vap;
    input vd;


    initial
        begin
        end

endmodule