vhdl.vhd

Cadence_Starter_Library

	\d2_mwe*\: OUT    STD_LOGIC;    
	\dma_dack0*\: OUT    STD_LOGIC;    
	\dma_dack1*\: OUT    STD_LOGIC;    
	\dma_dack2_lcs6*\: OUT    STD_LOGIC;    
	\dma_dack3_irq10*\: OUT    STD_LOGIC;    
	\dma_ddone0*\: OUT    STD_LOGIC;    
	\dma_ddone1*\: OUT    STD_LOGIC;    
	\dma_ddone2_lcs7*\: OUT    STD_LOGIC;    
	\dma_ddone3_irq11*\: OUT    STD_LOGIC;    
	\dma_dreq0*\: IN     STD_LOGIC;    
	\dma_dreq1*\: IN     STD_LOGIC;    
	\dma_dreq2_lcs5*\: IN     STD_LOGIC;    
	\dma_dreq3_irq9*\: IN     STD_LOGIC;    
	EC1_GTX_CLK125: IN     STD_LOGIC;    
	EC2_GTX_CLK125: IN     STD_LOGIC;    
	EC_MDC:    OUT    STD_LOGIC;    
	EC_MDIO:   INOUT  STD_LOGIC;    
	\hreset*\: IN     STD_LOGIC;    
	\hreset_req*\: OUT    STD_LOGIC;    
	IIC1_SCL:  INOUT  STD_LOGIC;    
	IIC1_SDA:  INOUT  STD_LOGIC;    
	IIC2_SCL:  INOUT  STD_LOGIC;    
	IIC2_SDA:  INOUT  STD_LOGIC;    
	IRQ0:      IN     STD_LOGIC;    
	IRQ1:      IN     STD_LOGIC;    
	IRQ2:      IN     STD_LOGIC;    
	IRQ3:      IN     STD_LOGIC;    
	IRQ4:      IN     STD_LOGIC;    
	IRQ5:      IN     STD_LOGIC;    
	IRQ6:      IN     STD_LOGIC;    
	IRQ7:      IN     STD_LOGIC;    
	IRQ8:      IN     STD_LOGIC;    
	\irq_out*\: OUT    STD_LOGIC;    
	LA27:      OUT    STD_LOGIC;    
	LA28:      OUT    STD_LOGIC;    
	LA29:      OUT    STD_LOGIC;    
	LA30:      OUT    STD_LOGIC;    
	LA31:      OUT    STD_LOGIC;    
	LAD0:      INOUT  STD_LOGIC;    
	LAD1:      INOUT  STD_LOGIC;    
	LAD10:     INOUT  STD_LOGIC;    
	LAD11:     INOUT  STD_LOGIC;    
	LAD12:     INOUT  STD_LOGIC;    
	LAD13:     INOUT  STD_LOGIC;    
	LAD14:     INOUT  STD_LOGIC;    
	LAD15:     INOUT  STD_LOGIC;    
	LAD16:     INOUT  STD_LOGIC;    
	LAD17:     INOUT  STD_LOGIC;    
	LAD18:     INOUT  STD_LOGIC;    
	LAD19:     INOUT  STD_LOGIC;    
	LAD2:      INOUT  STD_LOGIC;    
	LAD20:     INOUT  STD_LOGIC;    
	LAD21:     INOUT  STD_LOGIC;    
	LAD22:     INOUT  STD_LOGIC;    
	LAD23:     INOUT  STD_LOGIC;    
	LAD24:     INOUT  STD_LOGIC;    
	LAD25:     INOUT  STD_LOGIC;    
	LAD26:     INOUT  STD_LOGIC;    
	LAD27:     INOUT  STD_LOGIC;    
	LAD28:     INOUT  STD_LOGIC;    
	LAD29:     INOUT  STD_LOGIC;    
	LAD3:      INOUT  STD_LOGIC;    
	LAD30:     INOUT  STD_LOGIC;    
	LAD31:     INOUT  STD_LOGIC;    
	LAD4:      INOUT  STD_LOGIC;    
	LAD5:      INOUT  STD_LOGIC;    
	LAD6:      INOUT  STD_LOGIC;    
	LAD7:      INOUT  STD_LOGIC;    
	LAD8:      INOUT  STD_LOGIC;    
	LAD9:      INOUT  STD_LOGIC;    
	LALE:      OUT    STD_LOGIC;    
	LBCTL:     OUT    STD_LOGIC;    
	LCKE:      OUT    STD_LOGIC;    
	LCLK0:     OUT    STD_LOGIC;    
	LCLK1:     OUT    STD_LOGIC;    
	LCLK2:     OUT    STD_LOGIC;    
	\lcs0*\:   OUT    STD_LOGIC;    
	\lcs1*\:   OUT    STD_LOGIC;    
	\lcs2*\:   OUT    STD_LOGIC;    
	\lcs3*\:   OUT    STD_LOGIC;    
	\lcs4*\:   OUT    STD_LOGIC;    
	LDP0:      INOUT  STD_LOGIC;    
	LDP1:      INOUT  STD_LOGIC;    
	LDP2:      INOUT  STD_LOGIC;    
	LDP3:      INOUT  STD_LOGIC;    
	LGPL0_LSDA10: OUT    STD_LOGIC;    
	\lgpl1_lsdwe*\: OUT    STD_LOGIC;    
	\lgpl2_loe_ lsdras*\: OUT    STD_LOGIC;    
	\lgpl3_lsdcas*\: OUT    STD_LOGIC;    
	LGPL4_LGTA_LUPWAIT_LPBSE: INOUT  STD_LOGIC;    
	LGPL5:     OUT    STD_LOGIC;    
	\lssd_mode*\: IN     STD_LOGIC;    
	LSYNC_IN:  IN     STD_LOGIC;    
	LSYNC_OUT: OUT    STD_LOGIC;    
	\lwe_lsddqm_lbs0*\: OUT    STD_LOGIC;    
	\lwe_lsddqm_lbs1*\: OUT    STD_LOGIC;    
	\lwe_lsddqm_lbs2*\: OUT    STD_LOGIC;    
	\lwe_lsddqm_lbs3*\: OUT    STD_LOGIC;    
	\mcp_0*\:  IN     STD_LOGIC;    
	\mcp_1*\:  IN     STD_LOGIC;    
	READY_TRIG_OUT: OUT    STD_LOGIC;    
	RESERVED1: INOUT  STD_LOGIC;    
	RESERVED10: INOUT  STD_LOGIC;    
	RESERVED2: INOUT  STD_LOGIC;    
	RESERVED3: INOUT  STD_LOGIC;    
	RESERVED4: INOUT  STD_LOGIC;    
	RESERVED5: INOUT  STD_LOGIC;    
	RESERVED6: INOUT  STD_LOGIC;    
	RESERVED7: INOUT  STD_LOGIC;    
	RESERVED8: INOUT  STD_LOGIC;    
	RESERVED9: INOUT  STD_LOGIC;    
	RTC:       IN     STD_LOGIC;    
	SD1_DLL_TPA: INOUT  STD_LOGIC;    
	SD1_DLL_TPD: OUT    STD_LOGIC;    
	SD1_IMP_CAL_RX: INOUT  STD_LOGIC;    
	SD1_IMP_CAL_TX: INOUT  STD_LOGIC;    
	SD1_PLL_TPA: INOUT  STD_LOGIC;    
	SD1_PLL_TPD: OUT    STD_LOGIC;    
	SD1_REF_CLK: IN     STD_LOGIC;    
	\sd1_ref_clk*\: IN     STD_LOGIC;    
	SD1_RX0:   IN     STD_LOGIC;    
	\sd1_rx0*\: IN     STD_LOGIC;    
	SD1_RX1:   IN     STD_LOGIC;    
	\sd1_rx1*\: IN     STD_LOGIC;    
	SD1_RX2:   IN     STD_LOGIC;    
	\sd1_rx2*\: IN     STD_LOGIC;    
	SD1_RX3:   IN     STD_LOGIC;    
	\sd1_rx3*\: IN     STD_LOGIC;    
	SD1_RX4:   IN     STD_LOGIC;    
	\sd1_rx4*\: IN     STD_LOGIC;    
	SD1_RX5:   IN     STD_LOGIC;    
	\sd1_rx5*\: IN     STD_LOGIC;    
	SD1_RX6:   IN     STD_LOGIC;    
	\sd1_rx6*\: IN     STD_LOGIC;    
	SD1_RX7:   IN     STD_LOGIC;    
	\sd1_rx7*\: IN     STD_LOGIC;    
	SD1_TX0:   OUT    STD_LOGIC;    
	\sd1_tx0*\: OUT    STD_LOGIC;    
	SD1_TX1:   OUT    STD_LOGIC;    
	\sd1_tx1*\: OUT    STD_LOGIC;    
	SD1_TX2:   OUT    STD_LOGIC;    
	\sd1_tx2*\: OUT    STD_LOGIC;    
	SD1_TX3:   OUT    STD_LOGIC;    
	\sd1_tx3*\: OUT    STD_LOGIC;    
	SD1_TX4:   OUT    STD_LOGIC;    
	\sd1_tx4*\: OUT    STD_LOGIC;    
	SD1_TX5:   OUT    STD_LOGIC;    
	\sd1_tx5*\: OUT    STD_LOGIC;    
	SD1_TX6:   OUT    STD_LOGIC;    
	\sd1_tx6*\: OUT    STD_LOGIC;    
	SD1_TX7:   OUT    STD_LOGIC;    
	\sd1_tx7*\: OUT    STD_LOGIC;    
	SD2_DLL_TPA: INOUT  STD_LOGIC;    
	SD2_DLL_TPD: OUT    STD_LOGIC;    
	SD2_IMP_CAL_RX: INOUT  STD_LOGIC;    
	SD2_IMP_CAL_TX: INOUT  STD_LOGIC;    
	SD2_PLL_TPA: INOUT  STD_LOGIC;    
	SD2_PLL_TPD: OUT    STD_LOGIC;    
	SD2_REF_CLK: IN     STD_LOGIC;    
	\sd2_ref_clk*\: IN     STD_LOGIC;    
	SD2_RX0:   IN     STD_LOGIC;    
	\sd2_rx0*\: IN     STD_LOGIC;    
	SD2_RX1:   IN     STD_LOGIC;    
	\sd2_rx1*\: IN     STD_LOGIC;    
	SD2_RX2:   IN     STD_LOGIC;    
	\sd2_rx2*\: IN     STD_LOGIC;    
	SD2_RX3:   IN     STD_LOGIC;    
	\sd2_rx3*\: IN     STD_LOGIC;    
	SD2_RX4:   IN     STD_LOGIC;    
	\sd2_rx4*\: IN     STD_LOGIC;    
	SD2_RX5:   IN     STD_LOGIC;    
	\sd2_rx5*\: IN     STD_LOGIC;    
	SD2_RX6:   IN     STD_LOGIC;    
	\sd2_rx6*\: IN     STD_LOGIC;    
	SD2_RX7:   IN     STD_LOGIC;    
	\sd2_rx7*\: IN     STD_LOGIC;    
	SD2_TX0:   OUT    STD_LOGIC;    
	\sd2_tx0*\: OUT    STD_LOGIC;    
	SD2_TX1:   OUT    STD_LOGIC;    
	\sd2_tx1*\: OUT    STD_LOGIC;    
	SD2_TX2:   OUT    STD_LOGIC;    
	\sd2_tx2*\: OUT    STD_LOGIC;    
	SD2_TX3:   OUT    STD_LOGIC;    
	\sd2_tx3*\: OUT    STD_LOGIC;    
	SD2_TX4:   OUT    STD_LOGIC;    
	\sd2_tx4*\: OUT    STD_LOGIC;    
	SD2_TX5:   OUT    STD_LOGIC;    
	\sd2_tx5*\: OUT    STD_LOGIC;    
	SD2_TX6:   OUT    STD_LOGIC;    
	\sd2_tx6*\: OUT    STD_LOGIC;    
	SD2_TX7:   OUT    STD_LOGIC;    
	\sd2_tx7*\: OUT    STD_LOGIC;    
	SENSEVDD_CORE0: INOUT  STD_LOGIC;    
	SENSEVDD_CORE1: INOUT  STD_LOGIC;    
	SENSEVDD_PLAT: INOUT  STD_LOGIC;    
	SENSEVSS_CORE0: INOUT  STD_LOGIC;    
	SENSEVSS_CORE1: INOUT  STD_LOGIC;    
	SENSEVSS_PLAT: INOUT  STD_LOGIC;    
	\smi_0*\:  IN     STD_LOGIC;    
	\smi_1*\:  IN     STD_LOGIC;    
	SPARE:     INOUT  STD_LOGIC;    
	\sreset_0*\: IN     STD_LOGIC;    
	\sreset_1*\: IN     STD_LOGIC;    
	SYSCLK:    IN     STD_LOGIC;    
	TCK:       IN     STD_LOGIC;    
	TDI:       IN     STD_LOGIC;    
	TDO:       OUT    STD_LOGIC;    
	TEMP_ANODE: INOUT  STD_LOGIC;    
	TEMP_CATHODE: INOUT  STD_LOGIC;    
	TEST_MODE0: IN     STD_LOGIC;    
	TEST_MODE1: IN     STD_LOGIC;    
	TEST_MODE2: IN     STD_LOGIC;    
	TEST_MODE3: IN     STD_LOGIC;    
	TMS:       IN     STD_LOGIC;    
	TRIG_IN:   IN     STD_LOGIC;    
	\trst*\:   IN     STD_LOGIC;    
	TSEC1_COL: IN     STD_LOGIC;    
	TSEC1_CRS: INOUT  STD_LOGIC;    
	TSEC1_GTX_CLK: OUT    STD_LOGIC;    
	TSEC1_RX_CLK: IN     STD_LOGIC;    
	TSEC1_RX_DV: IN     STD_LOGIC;    
	TSEC1_RX_ER: IN     STD_LOGIC;    
	TSEC1_RXD0_GPIN0: IN     STD_LOGIC;    
	TSEC1_RXD1_GPIN1: IN     STD_LOGIC;    
	TSEC1_RXD2_GPIN2: IN     STD_LOGIC;    
	TSEC1_RXD3_GPIN3: IN     STD_LOGIC;    
	TSEC1_RXD4_GPIN4: IN     STD_LOGIC;    
	TSEC1_RXD5_GPIN5: IN     STD_LOGIC;    
	TSEC1_RXD6_GPIN6: IN     STD_LOGIC;    
	TSEC1_RXD7_GPIN7: IN     STD_LOGIC;    
	TSEC1_TX_CLK: IN     STD_LOGIC;    
	TSEC1_TX_EN: OUT    STD_LOGIC;    
	TSEC1_TX_ER: OUT    STD_LOGIC;    
	TSEC1_TXD0_GPOUT0: OUT    STD_LOGIC;    
	TSEC1_TXD1_GPOUT1: OUT    STD_LOGIC;    
	TSEC1_TXD2_GPOUT2: OUT    STD_LOGIC;    
	TSEC1_TXD3_GPOUT3: OUT    STD_LOGIC;    
	TSEC1_TXD4_GPOUT4: OUT    STD_LOGIC;    
	TSEC1_TXD5_GPOUT5: OUT    STD_LOGIC;    
	TSEC1_TXD6_GPOUT6: OUT    STD_LOGIC;    
	TSEC1_TXD7_GPOUT7: OUT    STD_LOGIC;    
	TSEC2_COL: IN     STD_LOGIC;    
	TSEC2_CRS: INOUT  STD_LOGIC;    
	TSEC2_GTX_CLK: OUT    STD_LOGIC;    
	TSEC2_RX_CLK: IN     STD_LOGIC;    
	TSEC2_RX_DV: IN     STD_LOGIC;    
	TSEC2_RX_ER: IN     STD_LOGIC;    
	TSEC2_RXD0_GPIN8: IN     STD_LOGIC;    
	TSEC2_RXD1_GPIN9: IN     STD_LOGIC;    
	TSEC2_RXD2_GPIN10: IN     STD_LOGIC;    
	TSEC2_RXD3_GPIN11: IN     STD_LOGIC;    
	TSEC2_RXD4_GPIN12: IN     STD_LOGIC;    
	TSEC2_RXD5_GPIN13: IN     STD_LOGIC;    
	TSEC2_RXD6_GPIN14: IN     STD_LOGIC;    
	TSEC2_RXD7_GPIN15: IN     STD_LOGIC;    
	TSEC2_TX_CLK: IN     STD_LOGIC;    
	TSEC2_TX_EN: OUT    STD_LOGIC;    
	TSEC2_TX_ER: OUT    STD_LOGIC;    
	TSEC2_TXD0_GPOUT8: OUT    STD_LOGIC;    
	TSEC2_TXD1_GPOUT9: OUT    STD_LOGIC;    
	TSEC2_TXD2_GPOUT10: OUT    STD_LOGIC;    
	TSEC2_TXD3_GPOUT11: OUT    STD_LOGIC;    
	TSEC2_TXD4_GPOUT12: OUT    STD_LOGIC;    
	TSEC2_TXD5_GPOUT13: OUT    STD_LOGIC;    
	TSEC2_TXD6_GPOUT14: OUT    STD_LOGIC;    
	TSEC2_TXD7_GPOUT15: OUT    STD_LOGIC;    
	TSEC3_COL: IN     STD_LOGIC;    
	TSEC3_CRS: INOUT  STD_LOGIC;    
	TSEC3_GTX_CLK: OUT    STD_LOGIC;    
	TSEC3_RX_CLK: IN     STD_LOGIC;    
	TSEC3_RX_DV: IN     STD_LOGIC;    
	TSEC3_RX_ER: IN     STD_LOGIC;    
	TSEC3_RXD0: IN     STD_LOGIC;    
	TSEC3_RXD1: IN     STD_LOGIC;    
	TSEC3_RXD2: IN     STD_LOGIC;    
	TSEC3_RXD3: IN     STD_LOGIC;    
	TSEC3_RXD4: IN     STD_LOGIC;    
	TSEC3_RXD5: IN     STD_LOGIC;    
	TSEC3_RXD6: IN     STD_LOGIC;    
	TSEC3_RXD7: IN     STD_LOGIC;    
	TSEC3_TX_CLK: IN     STD_LOGIC;    
	TSEC3_TX_EN: OUT    STD_LOGIC;    
	TSEC3_TX_ER: OUT    STD_LOGIC;    
	TSEC3_TXD0: OUT    STD_LOGIC;    
	TSEC3_TXD1: OUT    STD_LOGIC;    
	TSEC3_TXD2: OUT    STD_LOGIC;    
	TSEC3_TXD3: OUT    STD_LOGIC;    
	TSEC3_TXD4: OUT    STD_LOGIC;    
	TSEC3_TXD5: OUT    STD_LOGIC;    
	TSEC3_TXD6: OUT    STD_LOGIC;    
	TSEC3_TXD7: OUT    STD_LOGIC;    
	TSEC4_COL: IN     STD_LOGIC;    
	TSEC4_CRS: INOUT  STD_LOGIC;    
	TSEC4_GTX_CLK: OUT    STD_LOGIC;    
	TSEC4_RX_CLK: IN     STD_LOGIC;    
	TSEC4_RX_DV: IN     STD_LOGIC;    
	TSEC4_RX_ER: IN     STD_LOGIC;    
	TSEC4_RXD0: IN     STD_LOGIC;    
	TSEC4_RXD1: IN     STD_LOGIC;    
	TSEC4_RXD2: IN     STD_LOGIC;    
	TSEC4_RXD3: IN     STD_LOGIC;    
	TSEC4_RXD4: IN     STD_LOGIC;    
	TSEC4_RXD5: IN     STD_LOGIC;    
	TSEC4_RXD6: IN     STD_LOGIC;    
	TSEC4_RXD7: IN     STD_LOGIC;    
	TSEC4_TX_CLK: IN     STD_LOGIC;    
	TSEC4_TX_EN: OUT    STD_LOGIC;    
	TSEC4_TX_ER: OUT    STD_LOGIC;    
	TSEC4_TXD0: OUT    STD_LOGIC;    
	TSEC4_TXD1: OUT    STD_LOGIC;    
	TSEC4_TXD2: OUT    STD_LOGIC;    
	TSEC4_TXD3: OUT    STD_LOGIC;    
	TSEC4_TXD4: OUT    STD_LOGIC;    
	TSEC4_TXD5: OUT    STD_LOGIC;    
	TSEC4_TXD6: OUT    STD_LOGIC;    
	TSEC4_TXD7: OUT    STD_LOGIC;    
	\uart_cts0*\: IN     STD_LOGIC;    
	\uart_cts1*\: IN     STD_LOGIC;    
	\uart_rts0*\: OUT    STD_LOGIC;    
	\uart_rts1*\: OUT    STD_LOGIC;    
	UART_SIN0: IN     STD_LOGIC;    
	UART_SIN1: IN     STD_LOGIC;    
	UART_SOUT0: OUT    STD_LOGIC;    
	UART_SOUT1: OUT    STD_LOGIC);
end MPC8641D;