verilog.v

Cadence_Starter_Library

    inout d2_mdq49;
    inout d2_mdq5;
    inout d2_mdq50;
    inout d2_mdq51;
    inout d2_mdq52;
    inout d2_mdq53;
    inout d2_mdq54;
    inout d2_mdq55;
    inout d2_mdq56;
    inout d2_mdq57;
    inout d2_mdq58;
    inout d2_mdq59;
    inout d2_mdq6;
    inout d2_mdq60;
    inout d2_mdq61;
    inout d2_mdq62;
    inout d2_mdq63;
    inout d2_mdq7;
    inout d2_mdq8;
    inout d2_mdq9;
    inout d2_mdqs0;
    inout \d2_mdqs0* ;
    inout d2_mdqs1;
    inout \d2_mdqs1* ;
    inout d2_mdqs2;
    inout \d2_mdqs2* ;
    inout d2_mdqs3;
    inout \d2_mdqs3* ;
    inout d2_mdqs4;
    inout \d2_mdqs4* ;
    inout d2_mdqs5;
    inout \d2_mdqs5* ;
    inout d2_mdqs6;
    inout \d2_mdqs6* ;
    inout d2_mdqs7;
    inout \d2_mdqs7* ;
    inout d2_mdqs8;
    inout \d2_mdqs8* ;
    output d2_mdval;
    inout d2_mecc0;
    inout d2_mecc1;
    inout d2_mecc2;
    inout d2_mecc3;
    inout d2_mecc4;
    inout d2_mecc5;
    inout d2_mecc6;
    inout d2_mecc7;
    output d2_modt0;
    output d2_modt1;
    output d2_modt2;
    output d2_modt3;
    output \d2_mras* ;
    output d2_msrcid0;
    output d2_msrcid1;
    output d2_msrcid2;
    output d2_msrcid3;
    output d2_msrcid4;
    output d2_mvref;
    output \d2_mwe* ;
    output \dma_dack0* ;
    output \dma_dack1* ;
    output \dma_dack2_lcs6* ;
    output \dma_dack3_irq10* ;
    output \dma_ddone0* ;
    output \dma_ddone1* ;
    output \dma_ddone2_lcs7* ;
    output \dma_ddone3_irq11* ;
    input \dma_dreq0* ;
    input \dma_dreq1* ;
    input \dma_dreq2_lcs5* ;
    input \dma_dreq3_irq9* ;
    input ec1_gtx_clk125;
    input ec2_gtx_clk125;
    output ec_mdc;
    inout ec_mdio;
    input \hreset* ;
    output \hreset_req* ;
    inout iic1_scl;
    inout iic1_sda;
    inout iic2_scl;
    inout iic2_sda;
    input irq0;
    input irq1;
    input irq2;
    input irq3;
    input irq4;
    input irq5;
    input irq6;
    input irq7;
    input irq8;
    output \irq_out* ;
    output la27;
    output la28;
    output la29;
    output la30;
    output la31;
    inout lad0;
    inout lad1;
    inout lad10;
    inout lad11;
    inout lad12;
    inout lad13;
    inout lad14;
    inout lad15;
    inout lad16;
    inout lad17;
    inout lad18;
    inout lad19;
    inout lad2;
    inout lad20;
    inout lad21;
    inout lad22;
    inout lad23;
    inout lad24;
    inout lad25;
    inout lad26;
    inout lad27;
    inout lad28;
    inout lad29;
    inout lad3;
    inout lad30;
    inout lad31;
    inout lad4;
    inout lad5;
    inout lad6;
    inout lad7;
    inout lad8;
    inout lad9;
    output lale;
    output lbctl;
    output lcke;
    output lclk0;
    output lclk1;
    output lclk2;
    output \lcs0* ;
    output \lcs1* ;
    output \lcs2* ;
    output \lcs3* ;
    output \lcs4* ;
    inout ldp0;
    inout ldp1;
    inout ldp2;
    inout ldp3;
    output lgpl0_lsda10;
    output \lgpl1_lsdwe* ;
    output \lgpl2_loe_#20lsdras* ;
    output \lgpl3_lsdcas* ;
    inout lgpl4_lgta_lupwait_lpbse;
    output lgpl5;
    input \lssd_mode* ;
    input lsync_in;
    output lsync_out;
    output \lwe_lsddqm_lbs0* ;
    output \lwe_lsddqm_lbs1* ;
    output \lwe_lsddqm_lbs2* ;
    output \lwe_lsddqm_lbs3* ;
    input \mcp_0* ;
    input \mcp_1* ;
    output ready_trig_out;
    inout reserved1;
    inout reserved10;
    inout reserved2;
    inout reserved3;
    inout reserved4;
    inout reserved5;
    inout reserved6;
    inout reserved7;
    inout reserved8;
    inout reserved9;
    input rtc;
    inout sd1_dll_tpa;
    output sd1_dll_tpd;
    inout sd1_imp_cal_rx;
    inout sd1_imp_cal_tx;
    inout sd1_pll_tpa;
    output sd1_pll_tpd;
    input sd1_ref_clk;
    input \sd1_ref_clk* ;
    input sd1_rx0;
    input \sd1_rx0* ;
    input sd1_rx1;
    input \sd1_rx1* ;
    input sd1_rx2;
    input \sd1_rx2* ;
    input sd1_rx3;
    input \sd1_rx3* ;
    input sd1_rx4;
    input \sd1_rx4* ;
    input sd1_rx5;
    input \sd1_rx5* ;
    input sd1_rx6;
    input \sd1_rx6* ;
    input sd1_rx7;
    input \sd1_rx7* ;
    output sd1_tx0;
    output \sd1_tx0* ;
    output sd1_tx1;
    output \sd1_tx1* ;
    output sd1_tx2;
    output \sd1_tx2* ;
    output sd1_tx3;
    output \sd1_tx3* ;
    output sd1_tx4;
    output \sd1_tx4* ;
    output sd1_tx5;
    output \sd1_tx5* ;
    output sd1_tx6;
    output \sd1_tx6* ;
    output sd1_tx7;
    output \sd1_tx7* ;
    inout sd2_dll_tpa;
    output sd2_dll_tpd;
    inout sd2_imp_cal_rx;
    inout sd2_imp_cal_tx;
    inout sd2_pll_tpa;
    output sd2_pll_tpd;
    input sd2_ref_clk;
    input \sd2_ref_clk* ;
    input sd2_rx0;
    input \sd2_rx0* ;
    input sd2_rx1;
    input \sd2_rx1* ;
    input sd2_rx2;
    input \sd2_rx2* ;
    input sd2_rx3;
    input \sd2_rx3* ;
    input sd2_rx4;
    input \sd2_rx4* ;
    input sd2_rx5;
    input \sd2_rx5* ;
    input sd2_rx6;
    input \sd2_rx6* ;
    input sd2_rx7;
    input \sd2_rx7* ;
    output sd2_tx0;
    output \sd2_tx0* ;
    output sd2_tx1;
    output \sd2_tx1* ;
    output sd2_tx2;
    output \sd2_tx2* ;
    output sd2_tx3;
    output \sd2_tx3* ;
    output sd2_tx4;
    output \sd2_tx4* ;
    output sd2_tx5;
    output \sd2_tx5* ;
    output sd2_tx6;
    output \sd2_tx6* ;
    output sd2_tx7;
    output \sd2_tx7* ;
    inout sensevdd_core0;
    inout sensevdd_core1;
    inout sensevdd_plat;
    inout sensevss_core0;
    inout sensevss_core1;
    inout sensevss_plat;
    input \smi_0* ;
    input \smi_1* ;
    inout spare;
    input \sreset_0* ;
    input \sreset_1* ;
    input sysclk;
    input tck;
    input tdi;
    output tdo;
    inout temp_anode;
    inout temp_cathode;
    input test_mode0;
    input test_mode1;
    input test_mode2;
    input test_mode3;
    input tms;
    input trig_in;
    input \trst* ;
    input tsec1_col;
    inout tsec1_crs;
    output tsec1_gtx_clk;
    input tsec1_rx_clk;
    input tsec1_rx_dv;
    input tsec1_rx_er;
    input tsec1_rxd0_gpin0;
    input tsec1_rxd1_gpin1;
    input tsec1_rxd2_gpin2;
    input tsec1_rxd3_gpin3;
    input tsec1_rxd4_gpin4;
    input tsec1_rxd5_gpin5;
    input tsec1_rxd6_gpin6;
    input tsec1_rxd7_gpin7;
    input tsec1_tx_clk;
    output tsec1_tx_en;
    output tsec1_tx_er;
    output tsec1_txd0_gpout0;
    output tsec1_txd1_gpout1;
    output tsec1_txd2_gpout2;
    output tsec1_txd3_gpout3;
    output tsec1_txd4_gpout4;
    output tsec1_txd5_gpout5;
    output tsec1_txd6_gpout6;
    output tsec1_txd7_gpout7;
    input tsec2_col;
    inout tsec2_crs;
    output tsec2_gtx_clk;
    input tsec2_rx_clk;
    input tsec2_rx_dv;
    input tsec2_rx_er;
    input tsec2_rxd0_gpin8;
    input tsec2_rxd1_gpin9;
    input tsec2_rxd2_gpin10;
    input tsec2_rxd3_gpin11;
    input tsec2_rxd4_gpin12;
    input tsec2_rxd5_gpin13;
    input tsec2_rxd6_gpin14;
    input tsec2_rxd7_gpin15;
    input tsec2_tx_clk;
    output tsec2_tx_en;
    output tsec2_tx_er;
    output tsec2_txd0_gpout8;
    output tsec2_txd1_gpout9;
    output tsec2_txd2_gpout10;
    output tsec2_txd3_gpout11;
    output tsec2_txd4_gpout12;
    output tsec2_txd5_gpout13;
    output tsec2_txd6_gpout14;
    output tsec2_txd7_gpout15;
    input tsec3_col;
    inout tsec3_crs;
    output tsec3_gtx_clk;
    input tsec3_rx_clk;
    input tsec3_rx_dv;
    input tsec3_rx_er;
    input tsec3_rxd0;
    input tsec3_rxd1;
    input tsec3_rxd2;
    input tsec3_rxd3;
    input tsec3_rxd4;
    input tsec3_rxd5;
    input tsec3_rxd6;
    input tsec3_rxd7;
    input tsec3_tx_clk;
    output tsec3_tx_en;
    output tsec3_tx_er;
    output tsec3_txd0;
    output tsec3_txd1;
    output tsec3_txd2;
    output tsec3_txd3;
    output tsec3_txd4;
    output tsec3_txd5;
    output tsec3_txd6;
    output tsec3_txd7;
    input tsec4_col;
    inout tsec4_crs;
    output tsec4_gtx_clk;
    input tsec4_rx_clk;
    input tsec4_rx_dv;
    input tsec4_rx_er;
    input tsec4_rxd0;
    input tsec4_rxd1;
    input tsec4_rxd2;
    input tsec4_rxd3;
    input tsec4_rxd4;
    input tsec4_rxd5;
    input tsec4_rxd6;
    input tsec4_rxd7;
    input tsec4_tx_clk;
    output tsec4_tx_en;
    output tsec4_tx_er;
    output tsec4_txd0;
    output tsec4_txd1;
    output tsec4_txd2;
    output tsec4_txd3;
    output tsec4_txd4;
    output tsec4_txd5;
    output tsec4_txd6;
    output tsec4_txd7;
    input \uart_cts0* ;
    input \uart_cts1* ;
    output \uart_rts0* ;
    output \uart_rts1* ;
    input uart_sin0;
    input uart_sin1;
    output uart_sout0;
    output uart_sout1;


    initial
        begin
        end

endmodule