verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 20 行

// generated by newgenasym  Tue Nov 04 09:34:15 2008


module timer (cont, disch, gnd, out, reset, thres, trig, vcc);
    input cont;
    input disch;
    input gnd;
    output out;
    input reset;
    input thres;
    input trig;
    input vcc;


    initial
        begin
        end

endmodule