verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 33 行

// generated by newgenasym  Fri Oct 31 17:18:34 2008


module \74lvth373  (d1, d2, d3, d4, d5, d6, d7, d8, gnd, le, oe_n, q1, q2, q3, q4, q5,
        q6, q7, q8, vcc);
    input d1;
    input d2;
    input d3;
    input d4;
    input d5;
    input d6;
    input d7;
    input d8;
    input gnd;
    input le;
    output oe_n;
    output q1;
    output q2;
    output q3;
    output q4;
    output q5;
    output q6;
    output q7;
    output q8;
    input vcc;


    initial
        begin
        end

endmodule