verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 35 行

// generated by newgenasym  Fri Oct 31 19:08:47 2008


module \74lvth240  (a1_1, a1_2, a1_3, a1_4, a2_1, a2_2, a2_3, a2_4, epad, gnd,
        oe1_n, oe2_n, vcc, y1_1, y1_2, y1_3, y1_4, y2_1, y2_2, y2_3,
        y2_4);
    input a1_1;
    input a1_2;
    input a1_3;
    input a1_4;
    input a2_1;
    input a2_2;
    input a2_3;
    input a2_4;
    input epad;
    input gnd;
    output oe1_n;
    output oe2_n;
    input vcc;
    output y1_1;
    output y1_2;
    output y1_3;
    output y1_4;
    output y2_1;
    output y2_2;
    output y2_3;
    output y2_4;


    initial
        begin
        end

endmodule