verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Tue Nov 04 09:31:32 2008


module res4s (a, b);
    parameter    size = 1;
    inout [size-1:0] a;
    inout [size-1:0] b;


    initial
        begin
        end

endmodule