verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Tue Oct 28 09:37:56 2008


module respoti (a, b, t);
    inout a;
    inout b;
    inout t;


    initial
        begin
        end

endmodule