verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 17 行

// generated by newgenasym  Tue Dec 23 13:28:53 2008


module smb (a, b0, b1, b2, b3);
    inout a;
    inout b0;
    inout b1;
    inout b2;
    inout b3;


    initial
        begin
        end

endmodule