verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 16 行

// generated by newgenasym  Thu Oct 30 14:40:37 2008


module lt3080 (in, out1, out2, set);
    input in;
    output out1;
    output out2;
    input set;


    initial
        begin
        end

endmodule