verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 31 行

// generated by newgenasym  Thu Oct 23 15:04:42 2008


module ic574 (c1, d0, d1, d2, d3, d4, d5, d6, d7, en, o0, o1, o2, o3, o4, o5, o6,
        o7);
    input c1;
    input d0;
    input d1;
    input d2;
    input d3;
    input d4;
    input d5;
    input d6;
    input d7;
    output en;
    output o0;
    output o1;
    output o2;
    output o3;
    output o4;
    output o5;
    output o6;
    output o7;


    initial
        begin
        end

endmodule