verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 27 行

// generated by newgenasym  Tue Nov 04 09:34:48 2008


module \74lvth125  (a1, a2, a3, a4, gnd, oe1_n, oe2_n, oe3_n, oe4_n, vcc, y1, y2, y3,
        y4);
    input a1;
    input a2;
    input a3;
    input a4;
    input gnd;
    output oe1_n;
    output oe2_n;
    output oe3_n;
    output oe4_n;
    input vcc;
    output y1;
    output y2;
    output y3;
    output y4;


    initial
        begin
        end

endmodule