verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 56 行

// generated by newgenasym  Wed Oct 29 23:13:05 2008


module ltc4242c (auxfault1_n, auxfault2_n, auxin1, auxin2, auxon1, auxon2,
        auxout1, auxout2, auxpgood1_n, auxpgood2_n, en1_n, en2_n,
        epad, fault1_n, fault2_n, fon1, fon2, gnd, on1, on2, pgood1_n,
        pgood2_n, v12_gate1, v12_gate2, v12_in1, v12_in2, v12_out1,
        v12_out2, v12_sense1, v12_sense2, v3_gate1, v3_gate2,
        v3_in1, v3_in2, v3_out1, v3_out2, v3_sense1, v3_sense2, vcc);
    output auxfault1_n;
    output auxfault2_n;
    input auxin1;
    input auxin2;
    input auxon1;
    input auxon2;
    output auxout1;
    output auxout2;
    output auxpgood1_n;
    output auxpgood2_n;
    input en1_n;
    input en2_n;
    input epad;
    output fault1_n;
    output fault2_n;
    input fon1;
    input fon2;
    input gnd;
    input on1;
    input on2;
    output pgood1_n;
    output pgood2_n;
    input v12_gate1;
    input v12_gate2;
    input v12_in1;
    input v12_in2;
    output v12_out1;
    output v12_out2;
    input v12_sense1;
    input v12_sense2;
    input v3_gate1;
    input v3_gate2;
    input v3_in1;
    input v3_in2;
    output v3_out1;
    output v3_out2;
    input v3_sense1;
    input v3_sense2;
    input vcc;


    initial
        begin
        end

endmodule