verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 33 行

// generated by newgenasym  Wed Oct 29 23:15:07 2008


module \74lvth245  (a1, a2, a3, a4, a5, a6, a7, a8, b1, b2, b3, b4, b5, b6, b7, b8, dir,
        gnd, oe_n, vcc);
    input a1;
    input a2;
    input a3;
    input a4;
    input a5;
    input a6;
    input a7;
    input a8;
    output b1;
    output b2;
    output b3;
    output b4;
    output b5;
    output b6;
    output b7;
    output b8;
    input dir;
    input gnd;
    output oe_n;
    input vcc;


    initial
        begin
        end

endmodule