vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 29 行

-- generated by newgenasym Fri Oct 31 17:18:34 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvth373\ is
    port (    
	D1:        IN     STD_LOGIC;    
	D2:        IN     STD_LOGIC;    
	D3:        IN     STD_LOGIC;    
	D4:        IN     STD_LOGIC;    
	D5:        IN     STD_LOGIC;    
	D6:        IN     STD_LOGIC;    
	D7:        IN     STD_LOGIC;    
	D8:        IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	LE:        IN     STD_LOGIC;    
	OE_N:      OUT    STD_LOGIC;    
	Q1:        OUT    STD_LOGIC;    
	Q2:        OUT    STD_LOGIC;    
	Q3:        OUT    STD_LOGIC;    
	Q4:        OUT    STD_LOGIC;    
	Q5:        OUT    STD_LOGIC;    
	Q6:        OUT    STD_LOGIC;    
	Q7:        OUT    STD_LOGIC;    
	Q8:        OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC);
end \74lvth373\;