vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 30 行

-- generated by newgenasym Fri Oct 31 19:08:47 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \74lvth240\ is
    port (    
	A1_1:      IN     STD_LOGIC;    
	A1_2:      IN     STD_LOGIC;    
	A1_3:      IN     STD_LOGIC;    
	A1_4:      IN     STD_LOGIC;    
	A2_1:      IN     STD_LOGIC;    
	A2_2:      IN     STD_LOGIC;    
	A2_3:      IN     STD_LOGIC;    
	A2_4:      IN     STD_LOGIC;    
	EPAD:      IN     STD_LOGIC;    
	GND:       IN     STD_LOGIC;    
	OE1_N:     OUT    STD_LOGIC;    
	OE2_N:     OUT    STD_LOGIC;    
	VCC:       IN     STD_LOGIC;    
	Y1_1:      OUT    STD_LOGIC;    
	Y1_2:      OUT    STD_LOGIC;    
	Y1_3:      OUT    STD_LOGIC;    
	Y1_4:      OUT    STD_LOGIC;    
	Y2_1:      OUT    STD_LOGIC;    
	Y2_2:      OUT    STD_LOGIC;    
	Y2_3:      OUT    STD_LOGIC;    
	Y2_4:      OUT    STD_LOGIC);
end \74lvth240\;