verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 38 行

// generated by newgenasym  Thu Oct 30 21:46:29 2008


module ltc3713 (bg, boost, fcb, intvcc, ion, ith, pgnd1, pgnd2, pgood, \run/ss ,
        \sense+ , \sense- , sgnd1, sgnd2, shdn_n, sw1, sw2, tg, vfb1, vfb2,
        vin1, vin2, von, vring);
    inout bg;
    inout boost;
    input fcb;
    output intvcc;
    input ion;
    inout ith;
    input pgnd1;
    input pgnd2;
    output pgood;
    input \run/ss ;
    input \sense+ ;
    input \sense- ;
    input sgnd1;
    input sgnd2;
    inout shdn_n;
    inout sw1;
    inout sw2;
    inout tg;
    input vfb1;
    inout vfb2;
    input vin1;
    input vin2;
    input von;
    input vring;


    initial
        begin
        end

endmodule