vhdl.vhd

来自「Cadence_Starter_Library」· VHDL 代码 · 共 14 行

-- generated by newgenasym Tue Nov 04 09:31:32 2008

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity res4s is
    generic (
        size:positive:= 1
            );
    port (    
	A:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0);    
	B:         INOUT  STD_LOGIC_VECTOR (size-1 DOWNTO 0));
end res4s;