verilog.v

Cadence_Starter_Library

// generated by newgenasym  Fri Dec 19 00:01:13 2008


module fci_10061913_102clf (a1, a10, a11, a12, a13, a14, a15, a16, a17, a18, a19, a2, a20,
        a21, a22, a23, a24, a25, a26, a27, a28, a29, a3, a30, a31, a32,
        a33, a34, a35, a36, a37, a38, a39, a4, a40, a41, a42, a43, a44,
        a45, a46, a47, a48, a49, a5, a6, a7, a8, a9, b1, b10, b11, b12, b13,
        b14, b15, b16, b17, b18, b19, b2, b20, b21, b22, b23, b24, b25,
        b26, b27, b28, b29, b3, b30, b31, b32, b33, b34, b35, b36, b37,
        b38, b39, b4, b40, b41, b42, b43, b44, b45, b46, b47, b48, b49, b5,
        b6, b7, b8, b9);
    inout a1;
    inout a10;
    inout a11;
    inout a12;
    inout a13;
    inout a14;
    inout a15;
    inout a16;
    inout a17;
    inout a18;
    inout a19;
    inout a2;
    inout a20;
    inout a21;
    inout a22;
    inout a23;
    inout a24;
    inout a25;
    inout a26;
    inout a27;
    inout a28;
    inout a29;
    inout a3;
    inout a30;
    inout a31;
    inout a32;
    inout a33;
    inout a34;
    inout a35;
    inout a36;
    inout a37;
    inout a38;
    inout a39;
    inout a4;
    inout a40;
    inout a41;
    inout a42;
    inout a43;
    inout a44;
    inout a45;
    inout a46;
    inout a47;
    inout a48;
    inout a49;
    inout a5;
    inout a6;
    inout a7;
    inout a8;
    inout a9;
    inout b1;
    inout b10;
    inout b11;
    inout b12;
    inout b13;
    inout b14;
    inout b15;
    inout b16;
    inout b17;
    inout b18;
    inout b19;
    inout b2;
    inout b20;
    inout b21;
    inout b22;
    inout b23;
    inout b24;
    inout b25;
    inout b26;
    inout b27;
    inout b28;
    inout b29;
    inout b3;
    inout b30;
    inout b31;
    inout b32;
    inout b33;
    inout b34;
    inout b35;
    inout b36;
    inout b37;
    inout b38;
    inout b39;
    inout b4;
    inout b40;
    inout b41;
    inout b42;
    inout b43;
    inout b44;
    inout b45;
    inout b46;
    inout b47;
    inout b48;
    inout b49;
    inout b5;
    inout b6;
    inout b7;
    inout b8;
    inout b9;


    initial
        begin
        end

endmodule