verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 40 行

// generated by newgenasym  Fri Dec 19 00:01:14 2008


module dsub25gnd (mt1, mt2, p1, p10, p11, p12, p13, p14, p15, p16, p17, p18, p19,
        p2, p20, p21, p22, p23, p24, p25, p3, p4, p5, p6, p7, p8, p9);
    inout mt1;
    inout mt2;
    inout p1;
    inout p10;
    inout p11;
    inout p12;
    inout p13;
    inout p14;
    inout p15;
    inout p16;
    inout p17;
    inout p18;
    inout p19;
    inout p2;
    inout p20;
    inout p21;
    inout p22;
    inout p23;
    inout p24;
    inout p25;
    inout p3;
    inout p4;
    inout p5;
    inout p6;
    inout p7;
    inout p8;
    inout p9;


    initial
        begin
        end

endmodule