verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Tue Nov 04 09:42:24 2008


module ic_nand (in1, in2, out);
    input in1;
    input in2;
    output out;


    initial
        begin
        end

endmodule