verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Wed Oct 22 09:35:55 2008


module sw2c (c, o, s);
    inout c;
    inout o;
    inout s;


    initial
        begin
        end

endmodule