verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 16 行

// generated by newgenasym  Wed Oct 22 08:54:20 2008


module rec2p (ac1, ac2, m, p);
    inout ac1;
    inout ac2;
    inout m;
    inout p;


    initial
        begin
        end

endmodule