verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Thu Oct 23 15:10:38 2008


module trnchan (d, g, s);
    inout d;
    inout g;
    inout s;


    initial
        begin
        end

endmodule