verilog.v

来自「Cadence_Starter_Library」· Verilog 代码 · 共 15 行

// generated by newgenasym  Thu Oct 23 15:29:46 2008


module trpnp (b, c, e);
    inout b;
    inout c;
    inout e;


    initial
        begin
        end

endmodule