init.s

hyesco AT91RM9200 ucos-ii source code

;************************************************************************************************
;Compony:       CASIA
;File Name:		Init.s
;Description:		
;Author:		WeiAn	
;Date:			2004-03-11
;*************************CONST DEFINATION******************************************************/	
AT91C_BASE_CKGR       EQU  0xFFFFFC20      
AT91C_CKGR_MOSCEN     EQU  0x1
AT91C_CKGR_OSCOUNT    EQU  0x0ff00
CKGR_MOR              EQU  0xFFFFFC20

AT91_USER_Stack_Begin EQU  0x21000000
AT91_Stack_Begin      EQU  0x21000000

ARM_MODE_USER         EQU  0x10
ARM_MODE_FIQ          EQU  0x11
ARM_MODE_IRQ          EQU  0x12
ARM_MODE_SVC          EQU  0x13
ARM_MODE_ABORT        EQU  0x17
ARM_MODE_UNDEF        EQU  0x1B
ARM_MODE_SYS          EQU  0x1F
ARM_MODE_MASK         EQU  0x1F

I_BIT                 EQU  0x80
F_BIT                 EQU  0x40
T_BIT                 EQU  0x20

IRQ_STACK_SIZE		  EQU  0x10
FIQ_STACK_SIZE		  EQU  0x04
ABT_STACK_SIZE		  EQU  0x04
UND_STACK_SIZE		  EQU  0x04
SVC_STACK_SIZE		  EQU  0x10
USER_STACK_SIZE		  EQU  0x400


AT91C_BASE_AIC        EQU  0xFFFFF000     
AT91C_AIC_IVR         EQU  0xFFFFF100
AT91C_AIC_EOICR       EQU  0xFFFFF130
;*************************REGISTER DEFINATION*****************************************************/
AT91C_AIC_IMR              EQU  0xfffff110


;*************************************************************************************************/
    CODE32
	AREA    	Init,CODE,READONLY
	ENTRY 
       
                B          Reset_Handler

undefvec        B          undefvec

swivec          B          swivec   

pabtvec         B          pabtvec  

dabtvec         B          dabtvec 

rsvdvec         B          rsvdvec  

irqvec          ldr         pc, [pc,#-0xF20]

fiqvec          ldr         pc, [pc,#-0xF20]   


Reset_Handler


;******************************************
;Disable All Interrupt
;******************************************
          ldr r0,=AT91C_AIC_IMR
          ldr r1,=0
          STR r1,[r0]

; Get the CKGR Base Address
	ldr     r1, = AT91C_BASE_CKGR	
	
;-Main oscillator Enable register	APMC_MOR : Enable main oscillator , OSCOUNT = 0xFF
;	ldr 	r0, = AT91C_CKGR_MOSCEN:OR:AT91C_CKGR_OSCOUNT
	ldr 	r0, =0x0000FF01
	str     r0, [r1, #CKGR_MOR]

;**************************************
;Low level Init (PMC, AIC, EBI, ....)
;**************************************

;- Add loop to compensate Main Oscillator startup time
	ldr 	r0, =0x00000010
LoopOsc
	subs    r0, r0, #1              
	bhi     LoopOsc
	
	ldr 	r1, = 0x00204000	

;- Set up Supervisor Mode and set SVC Stack
	;msr     cpsr_c, #(ARM_MODE_SVC | I_BIT | F_BIT)
;Insure word alignement
	bic     r1, r1, #3                  
; Init stack SYS	
	mov     sp, r1                      
	IMPORT AT91F_LowLevelInit
	bl AT91F_LowLevelInit
	

;*****************************************
; Read/modify/write CP15 control register 
;*****************************************
; read cp15 control registre (cp15 r1) in r0
    mrc     p15, 0, r0, c1, c0, 0
; Reset bit :Little Endian end fast bus mode
    ldr     r3, =0xC0000080      
; Set bit :Asynchronous clock mode, Not Fast Bus
    ldr     r4, =0xC0000000      
    bic     r0, r0, r3             
    orr     r0, r0, r4             
; write r0 in cp15 control registre (cp15 r1)
    mcr     p15, 0, r0, c1, c0, 0 

;*******************************************
; Setup the stack for each mode
;*******************************************
   ldr		r0, =AT91_Stack_Begin

;Set up Undefined Instruction Mode and set Undef Mode Stack
	msr     CPSR_c, #(ARM_MODE_UNDEF | I_BIT | F_BIT)
;Init stack Undef
	mov     r13, r0 
	sub     r0, r0, #UND_STACK_SIZE
	
;Set up Abort Mode and set Abort Mode Stack
	msr     CPSR_c, #(ARM_MODE_ABORT | I_BIT | F_BIT)
;Init stack Abort
	mov     r13, r0
	sub     r0, r0, #ABT_STACK_SIZE
	
;Set up Interrupt Mode and set IRQ Mode Stack
	msr     CPSR_c, #(ARM_MODE_IRQ | I_BIT | F_BIT)
;Init stack IRQ
	mov     r13, r0                     
	sub     r0, r0, #IRQ_STACK_SIZE
	
;Set up Fast Interrupt Mode and set FIQ Mode Stack
	msr     CPSR_c, #(ARM_MODE_FIQ | I_BIT | F_BIT)
;Init stack FIQ
	mov     r13, r0
	sub     r0, r0, #FIQ_STACK_SIZE

	
;Set up Supervisor Mode and set SVC Mode Stack
	msr     CPSR_c, #(ARM_MODE_SVC | F_BIT)
;Init stack Sup
	mov     r13, r0                     
 	sub     r0, r0, #SVC_STACK_SIZE


 


	


;Set up User Mode, set User Mode Stack and enable interrupts  
	;msr     CPSR_c, #(ARM_MODE_SYS | F_BIT)
; Init stack User
	;mov     r13, r0

; change to user mode 
   ;mrs     r0    , CPSR
   ;bic     r0,r0, #I_BIT
   ;msr     CPSR_c, r0
   ;msr     cpsr_fsxc, #ARM_MODE_SVC   
;********************************************************************
; End of Stack Setup
;********************************************************************
;*********************************
;Copy Armboot form flash to sdram
;*********************************
;source address
     ;ldr	r0, =Armboot_begin
;size of armboot(20K)	
	;ldr	r2, =0x5000		
;target address(start of sdram)
	;ldr	r1, =0x20000000 
    
;copy begin here	
;rom2ram_copy
    ;subs r2, r2, #1
    ;ldr	r3, [r0],#4
    ;str	r3, [r1],#4
    ;bne	rom2ram_copy
;Jump to target address
    ;ldr    	r0,=0x20000000
    ;mov    	pc,r0
   
;Armboot_begin


;*****************************************************************************         
;Jump to Main Routine	
	  IMPORT      C_Entry	
      BL      	  C_Entry
Halt  B  Halt
      END