_primary.vhd

来自「AM2900模块中的微地址选址单元」· VHDL 代码 · 共 11 行

library verilog;
use verilog.vl_types.all;
entity Upc_AM is
    port(
        clk_i           : in     vl_logic;
        cin_i           : in     vl_logic;
        d_in_i          : in     vl_logic_vector(11 downto 0);
        upc_data_o      : out    vl_logic_vector(11 downto 0)
    );
end Upc_AM;