_primary.vhd

来自「AM2900模块中的微地址选址单元」· VHDL 代码 · 共 47 行

library verilog;
use verilog.vl_types.all;
entity control_AM is
    generic(
        JZ              : integer := 0;
        CJS             : integer := 1;
        JMAP            : integer := 2;
        CJP             : integer := 3;
        PUSH            : integer := 4;
        JSRP            : integer := 5;
        CJV             : integer := 6;
        JRP             : integer := 7;
        RFCT            : integer := 8;
        RPCT            : integer := 9;
        CRTN            : integer := 10;
        CJPP            : integer := 11;
        LDCT            : integer := 12;
        \LOOP\          : integer := 13;
        CONT            : integer := 14;
        TWB             : integer := 15;
        HOLD_STK        : integer := 0;
        CLEAR_STK       : integer := 1;
        POP_STK         : integer := 3;
        PUSH_STK        : integer := 2;
        HOLD_R_CON      : integer := 0;
        DEC_R_CON       : integer := 3;
        LOAD_R_CON      : integer := 1;
        MUX_CLEAR       : integer := 4;
        MUX_REG_DATA    : integer := 0;
        MUX_DATA        : integer := 1;
        MUX_STK_DATA    : integer := 3;
        MUX_UPC_DATA    : integer := 2
    );
    port(
        zero_i          : in     vl_logic;
        cond_code_i     : in     vl_logic;
        con_code_enable_i: in     vl_logic;
        inst_i          : in     vl_logic_vector(3 downto 0);
        reg_cnt_o       : out    vl_logic_vector(1 downto 0);
        mux_cnt_o       : out    vl_logic_vector(2 downto 0);
        stk_cnt_o       : out    vl_logic_vector(1 downto 0);
        map_bar_o       : out    vl_logic;
        pl_bar_o        : out    vl_logic;
        vect_bar_o      : out    vl_logic
    );
end control_AM;