_primary.vhd

AM2900模块中的微地址选址单元

library verilog;
use verilog.vl_types.all;
entity top_AM is
    port(
        OE_I            : in     vl_logic;
        RLD_I           : in     vl_logic;
        D_I             : in     vl_logic_vector(11 downto 0);
        CLK_I           : in     vl_logic;
        CC_I            : in     vl_logic;
        CCEN_I          : in     vl_logic;
        I_I             : in     vl_logic_vector(3 downto 0);
        CIN_I           : in     vl_logic;
        FULL_O          : out    vl_logic;
        Y_O             : out    vl_logic_vector(11 downto 0);
        MAP_BAR_O       : out    vl_logic;
        PL_BAR_O        : out    vl_logic;
        VECT_BAR_O      : out    vl_logic
    );
end top_AM;