_primary.vhd

AM2900模块中的微地址选址单元

library verilog;
use verilog.vl_types.all;
entity Mux_Out_AM is
    generic(
        CLEAR           : integer := 4;
        REG_DATA        : integer := 0;
        DATA            : integer := 1;
        STK_DATA        : integer := 3;
        UPC_DATA        : integer := 2
    );
    port(
        enable_i        : in     vl_logic;
        reg_data_i      : in     vl_logic_vector(11 downto 0);
        data_i          : in     vl_logic_vector(11 downto 0);
        sel_i           : in     vl_logic_vector(2 downto 0);
        stk_data_i      : in     vl_logic_vector(11 downto 0);
        upc_data_i      : in     vl_logic_vector(11 downto 0);
        data_out_o      : out    vl_logic_vector(11 downto 0);
        mux_out_o       : out    vl_logic_vector(11 downto 0)
    );
end Mux_Out_AM;