2410lib.c

基于Verilog HDL的电梯系统设计

//===================================================================
// File Name : 2410lib.c
// Function  : S3C2410 PLL,Uart, LED, Port Init
// Program   : Shin, On Pil (SOP)
// Date      : May 14, 2002
// Version   : 0.0
// History
//   0.0 : Programming start (February 20,2002) -> SOP
//===================================================================

#include "def.h"
#include "option.h"
#include "2410addr.h"
#include "2410lib.h"
#include "2410slib.h" 

#include <stdarg.h>
#include <string.h>
#include <stdlib.h>
#include <stdio.h>
#include <ctype.h>

extern char Image$$RW$$Limit[];
void *mallocPt=Image$$RW$$Limit;

//===========================[ SYSTEM ]===================================================
//static int delayLoopCount = 400;
static int delayLoopCount = FCLK/10000/10;

void Delay(int time)
{
      // time=0: adjust the Delay function by WatchDog timer.
      // time>0: the number of loop time
      // resolution of time is 100us.
    int i,adjust=0;
    if(time==0)
    {
        time   = 200;
        adjust = 1;
        delayLoopCount = 400;
            //PCLK/1M,Watch-dog disable,1/64,interrupt disable,reset disable
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3); 
        rWTDAT = 0xffff;                              //for first update
        rWTCNT = 0xffff;                              //resolution=64us @any PCLK 
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3)|(1<<5); //Watch-dog timer start
    }
    for(;time>0;time--)
        for(i=0;i<delayLoopCount;i++);
    if(adjust==1)
    {
        rWTCON = ((PCLK/1000000-1)<<8)|(2<<3);   //Watch-dog timer stop
        i = 0xffff - rWTCNT;                     //1count->64us, 200*400 cycle runtime = 64*i us
        delayLoopCount = 8000000/(i*64);         //200*400:64*i=1*x:100 -> x=80000*100/(64*i)   
    }
}

//===========================[ PORTS ]===================================================*
void Port_Init(void)
{
    //CAUTION:Follow the configuration order for setting the ports. 
    // 1) setting value(GPnDAT) 
    // 2) setting control register  (GPnCON)
    // 3) configure pull-up resistor(GPnUP)  

    //32bit data bus configuration  
    //=== PORT A GROUP
    //Ports  : GPA22 GPA21  GPA20 GPA19 GPA18 GPA17 GPA16 GPA15 GPA14 GPA13 GPA12  
    //Signal : nFCE nRSTOUT nFRE   nFWE  ALE   CLE  nGCS5 nGCS4 nGCS3 nGCS2 nGCS1 
    //Binary :  1     1      1  , 1   1   1    1   ,  1     1     1     1
    //Ports  : GPA11   GPA10  GPA9   GPA8   GPA7   GPA6   GPA5   GPA4   GPA3   GPA2   GPA1  GPA0
    //Signal : ADDR26 ADDR25 ADDR24 ADDR23 ADDR22 ADDR21 ADDR20 ADDR19 ADDR18 ADDR17 ADDR16 ADDR0 
    //Binary :  1       1      1      1   , 1       1      1      1   ,  1       1     1      1         
    rGPACON = 0x7fffff; 

    //===* PORT B GROUP
    //Ports  : GPB10    GPB9    GPB8    GPB7    GPB6     GPB5    GPB4   GPB3   GPB2     GPB1      GPB0
    //Signal : nXDREQ0 nXDACK0 nXDREQ1 nXDACK1 nSS_KBD nDIS_OFF L3CLOCK L3DATA L3MODE nIrDATXDEN Keyboard
    //Setting: INPUT  OUTPUT   INPUT  OUTPUT   INPUT   OUTPUT   OUTPUT OUTPUT OUTPUT   OUTPUT    OUTPUT 
    //Binary :   00  ,  01       00  ,   01      00   ,  01       01  ,   01     01   ,  01        01  
    rGPBCON = 0x044555;
    rGPBUP  = 0x7ff;     // The pull up function is disabled GPB[10:0]

    //=== PORT C GROUP
    //Ports  : GPC15 GPC14 GPC13 GPC12 GPC11 GPC10 GPC9 GPC8  GPC7   GPC6   GPC5 GPC4 GPC3  GPC2  GPC1 GPC0
    //Signal : VD7   VD6   VD5   VD4   VD3   VD2   VD1  VD0 LCDVF2 LCDVF1 LCDVF0 VM VFRAME VLINE VCLK LEND  
    //Binary :  10   10  , 10    10  , 10    10  , 10   10  , 10     10  ,  10   10 , 10     10 , 10   10
    rGPCCON = 0xaaaaaaaa;       
    rGPCUP  = 0xffff;     // The pull up function is disabled GPC[15:0] 

    //=== PORT D GROUP
    //Ports  : GPD15 GPD14 GPD13 GPD12 GPD11 GPD10 GPD9 GPD8 GPD7 GPD6 GPD5 GPD4 GPD3 GPD2 GPD1 GPD0
    //Signal : VD23  VD22  VD21  VD20  VD19  VD18  VD17 VD16 VD15 VD14 VD13 VD12 VD11 VD10 VD9  VD8
    //Binary : 10    10  , 10    10  , 10    10  , 10   10 , 10   10 , 10   10 , 10   10 ,10   10
    rGPDCON = 0xaaaaaaaa;       
    rGPDUP  = 0xffff;     // The pull up function is disabled GPD[15:0]

    //=== PORT E GROUP
    //Ports  : GPE15  GPE14 GPE13   GPE12   GPE11   GPE10   GPE9    GPE8     GPE7  GPE6  GPE5   GPE4  
    //Signal : IICSDA IICSCL SPICLK SPIMOSI SPIMISO SDDATA3 SDDATA2 SDDATA1 SDDATA0 SDCMD SDCLK I2SSDO 
    //Binary :  10     10  ,  10      10  ,  10      10   ,  10      10   ,   10    10  , 10     10  ,     
    //-------------------------------------------------------------------------------------------------------
    //Ports  :  GPE3   GPE2  GPE1    GPE0    
    //Signal : I2SSDI CDCLK I2SSCLK I2SLRCK     
    //Binary :  10     10  ,  10      10 
    rGPECON = 0xaaaaaaaa;       
    rGPEUP  = 0xffff;     // The pull up function is disabled GPE[15:0]

    //=== PORT F GROUP
    //Ports  : GPF7   GPF6   GPF5   GPF4      GPF3     GPF2  GPF1   GPF0
    //Signal : nLED_8 nLED_4 nLED_2 nLED_1 nIRQ_PCMCIA EINT2 KBDINT EINT0
    //Setting: Output Output Output Output    EINT3    EINT2 EINT1  EINT0
    //Binary :  01      01 ,  01     01  ,     10       10  , 10     10
    rGPFCON = 0x5582;
    rGPFUP  = 0xff;     // The pull up function is disabled GPF[7:0]

    //=== PORT G GROUP
    //Ports  : GPG15 GPG14 GPG13 GPG12 GPG11    GPG10    GPG9     GPG8     GPG7      GPG6    
    //Signal : nYPON  YMON nXPON XMON  EINT19 DMAMODE1 DMAMODE0 DMASTART KBDSPICLK KBDSPIMOSI
    //Setting: nYPON  YMON nXPON XMON  EINT19  Output   Output   Output   SPICLK1    SPIMOSI1
    //Binary :   11    11 , 11    11  , 10      01    ,   01       01   ,    11         11
    //-----------------------------------------------------------------------------------------
    //Ports  :    GPG5       GPG4    GPG3    GPG2    GPG1    GPG0    
    //Signal : KBDSPIMISO LCD_PWREN EINT11 nSS_SPI IRQ_LAN IRQ_PCMCIA
    //Setting:  SPIMISO1  LCD_PWRDN EINT11   nSS0   EINT9    EINT8
    //Binary :     11         11   ,  10      11  ,  10        10
    rGPGCON = 0xff95ffba;
    rGPGUP  = 0xffff;    // The pull up function is disabled GPG[15:0]

/*    
    //GPG4 Output Port [9:8] 01      -> LCD_PWREN Enable
    rGPGCON = (rGPGCON & 0xfffffcff) | (1<<8);
    rGPGDAT = (rGPGDAT & 0xffef) | (1<<4);
*/
    //=== PORT H GROUP
    //Ports  :  GPH10    GPH9  GPH8 GPH7  GPH6  GPH5 GPH4 GPH3 GPH2 GPH1  GPH0 
    //Signal : CLKOUT1 CLKOUT0 UCLK nCTS1 nRTS1 RXD1 TXD1 RXD0 TXD0 nRTS0 nCTS0
    //Binary :   10   ,  10     10 , 11    11  , 10   10 , 10   10 , 10    10
    rGPHCON = 0x2afaaa;
    rGPHUP  = 0x7ff;    // The pull up function is disabled GPH[10:0]
    
    //External interrupt will be falling edge triggered. 
    rEXTINT0 = 0x22222222;    // EINT[7:0]
    rEXTINT1 = 0x22222222;    // EINT[15:8]
    rEXTINT2 = 0x22222222;    // EINT[23:16]
}


//===========================[ UART ]==============================
static int whichUart=0;

void Uart_Init(int pclk,int baud)
{
    int i;
    
    if(pclk == 0)
    pclk    = PCLK;
    rUFCON0 = 0x0;   //UART channel 0 FIFO control register, FIFO disable
    rUFCON1 = 0x0;   //UART channel 1 FIFO control register, FIFO disable
    rUFCON2 = 0x0;   //UART channel 2 FIFO control register, FIFO disable
    rUMCON0 = 0x0;   //UART chaneel 0 MODEM control register, AFC disable
    rUMCON1 = 0x0;   //UART chaneel 1 MODEM control register, AFC disable
    
//UART0
/*	ULCON0 0x50000000 R/W UART channel 0 line control register 0x00
	Reserved 		[7]
	lnfra-Red Mode	[6]		Determine whether or not to use lnfra-Red mode
							0 = Normal mode operation 1 = lnfra-Red Tx/Rx mode
	Parity Mode		[5:3]	Specify the type of parity generation and cheking during UART transmit and receive operation
							0xx = No parity	100 = Odd parity	101 = Even parity
							110 = Parity forced/checked as 1
							111 = Parity forced/checked as 0
	Number of Stop Bit	[2]		Specify how many stop bits are to be used for end-of-frame signal
							0 = One stop bit per frame
							1 = Two stop bit per frame
	Word Length		[1:0]	Indicate the number of data bits to be transmitted or received per frame
							00 = 5-bit	01 = 6-bit	10 = 7-bit	11 = 8 - bit
*/
    rULCON0 = 0x3;   //Line control register : Normal,No parity,1 stop,8 bits
/*	UCON0 0x50000004 R/W UART channel 0 control register 0x00
	Clock Selection	[10]		Select PCLK or UEXTCLK for the UART baud rate
							0 = PCLK 	: UBRDIVn = (int)(PCLK/(bps*16)) - 1
							1 = UEXTCLK	: UBRDIVn = (int)(UEXTClK/(bps*16)) -1
	Tx Interrupt Type	[9]		Interrupt request type
							0 = Pulse(Interrupt is request as soon as the Tx buffer becomes empty in Non-FIFO mode
									or reaches Tx FIFO Trigger Level FIFO mode)
							1 = Level(Interrupt is requested while Tx buffer is empty in Non-FIFO mode
									or reaches Tx FIFO Trigger Level in FIFO mode)
	Rx Interrupt Type	[8]		Interrupt request type
							0 = Pulse(Interrupt is request as soon as the Rx buffer becomes empty in Non-FIFO mode
									or reaches Rx FIFO Trigger Level FIFO mode)
							1 = Level(Interrupt is requested while Tx buffer is empty in Non-FIFO mode
									or reaches Rx FIFO Trigger Level in FIFO mode)
	Rx Time Out		[7]		Enable/Disable Rx time out interrupt when UART FIFO is enable
	Enable						The interript is a receive interrupt
							0 = Disable 1 = Enable
	Rx Error Status	[6]		Enable the UART to generate an interript upon an exception, such as a frame error,
	Interrupt Enable			or overrun error during a receive operation
							0 = Do not generate receive error status interrupt
							1 = Generate receive error status interrupt
	Loopback Mode	[5]		Setting loopback bit to 1 causes the UART to enter loopback mode,
							This mode is provied for test purpose only
							0 = Normal operation	1 = Loopback mode
	Reserved			[4]		Reserved
	Transmit Mode	[3:2]	Determine which fuction is currently able to write Tx data to the 
							UART transmit buffer register(UART Tx Enable/Disable)
							00 == Disable
							01 = Interrupt request or polling mode
							10 = DMA0 request(Only for UART0)
								 DMA3 request(Only for UART2)
							11 = DMA1 request(Only for UART1)
	Receive Mode		[1:0]	Determine which fuction is currently able to read data from the 
							UART Receive buffer register(UART Rx Enable/Disable)
							00 == Disable
							01 = Interrupt request or polling mode
							10 = DMA0 request(Only for UART0)
								 DMA3 request(Only for UART2)
							11 = DMA1 request(Only for UART1)
*/
    rUCON0  = 0x245;                        // Control register
//    rUBRDIV0=( (int)(pclk/16./baud) -1 );   //Baud rate divisior register 0
    rUBRDIV0=( (int)(pclk/16./baud+0.5) -1 );   //Baud rate divisior register 0    
    
//UART1
    rULCON1 = 0x3;
    rUCON1  = 0x245;
    rUBRDIV1=( (int)(pclk/16./baud) -1 );
    
//UART2
    rULCON2 = 0x3;
    rUCON2  = 0x245;
    rUBRDIV2=( (int)(pclk/16./baud) -1 );    

    for(i=0;i<100;i++);	
}

//===================================================================
void Uart_Select(int ch)
{
    whichUart = ch;
}

//===================================================================
void Uart_TxEmpty(int ch)
{
    if(ch==0)
        while(!(rUTRSTAT0 & 0x4)); //Wait until tx shifter is empty.
          
    else if(ch==1)
        while(!(rUTRSTAT1 & 0x4)); //Wait until tx shifter is empty.
        
    else if(ch==2)
        while(!(rUTRSTAT2 & 0x4)); //Wait until tx shifter is empty.
}

//=====================================================================
char Uart_Getch(void)
{
    if(whichUart==0)
    {       
        while(!(rUTRSTAT0 & 0x1)); //Receive data ready
        return RdURXH0();
    }
    else if(whichUart==1)
    {       
        while(!(rUTRSTAT1 & 0x1)); //Receive data ready
        return RdURXH1();
    }
    else if(whichUart==2)
    {
        while(!(rUTRSTAT2 & 0x1)); //Receive data ready
        return RdURXH2();
    }