tx.v

nios系统下LVDS的ip源码

// megafunction wizard: %ALTLVDS%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altlvds_tx 

// ============================================================
// File Name: tx.v
// Megafunction Name(s):
// 			altlvds_tx
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1.18 SJ Full Version
// ************************************************************


//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files any of the foregoing 
//(including device programming or simulation files), and any 
//associated documentation or information are expressly subject 
//to the terms and conditions of the Altera Program License 
//Subscription Agreement, Altera MegaCore Function License 
//Agreement, or other applicable license agreement, including, 
//without limitation, that your use is for the sole purpose of 
//programming logic devices manufactured by Altera and sold by 
//Altera or its authorized distributors.  Please refer to the 
//applicable agreement for further details.


// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module tx (
	tx_in,
	tx_inclock,
	tx_out);

	input	[7:0]  tx_in;
	input	  tx_inclock;
	output	[0:0]  tx_out;

	wire [0:0] sub_wire0;
	wire [0:0] tx_out = sub_wire0[0:0];

	altlvds_tx	altlvds_tx_component (
				.tx_in (tx_in),
				.tx_inclock (tx_inclock),
				.tx_out (sub_wire0)
				// synopsys translate_off
				,
				.pll_areset (),
				.sync_inclock (),
				.tx_coreclock (),
				.tx_enable (),
				.tx_locked (),
				.tx_outclock (),
				.tx_pll_enable ()
				// synopsys translate_on
				);
	defparam
		altlvds_tx_component.deserialization_factor = 8,
		altlvds_tx_component.implement_in_les = "OFF",
		altlvds_tx_component.intended_device_family = "Cyclone II",
		altlvds_tx_component.lpm_type = "altlvds_tx",
		altlvds_tx_component.number_of_channels = 1,
		altlvds_tx_component.registered_input = "OFF",
		altlvds_tx_component.use_external_pll = "ON";


endmodule

// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "8"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Ext_PLL STRING "ON"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: Int_Device STRING "Cyclone II"
// Retrieval info: PRIVATE: LVDS_Mode NUMERIC "0"
// Retrieval info: PRIVATE: Num_Channel NUMERIC "1"
// Retrieval info: CONSTANT: DESERIALIZATION_FACTOR NUMERIC "8"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altlvds_tx"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "OFF"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "ON"
// Retrieval info: USED_PORT: tx_in 0 0 8 0 INPUT NODEFVAL tx_in[7..0]
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT_CLK_EXT GND tx_inclock
// Retrieval info: USED_PORT: tx_out 0 0 1 0 OUTPUT NODEFVAL tx_out[0..0]
// Retrieval info: CONNECT: @tx_in 0 0 8 0 tx_in 0 0 8 0
// Retrieval info: CONNECT: tx_out 0 0 1 0 @tx_out 0 0 1 0
// Retrieval info: CONNECT: @tx_inclock 0 0 0 0 tx_inclock 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL tx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx.inc TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx.cmp TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx.bsf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL tx_bb.v TRUE