lvds.map.rpt

nios系统下LVDS的ip源码

Analysis & Synthesis report for lvds
Tue Nov 07 03:09:18 2006
Version 6.0 Build 202 06/20/2006 Service Pack 1.18 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis RAM Summary
  8. Registers Protected by Synthesis
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Source assignments for tx:b2v_inst|altlvds_tx:altlvds_tx_component
 13. Source assignments for tx:b2v_inst|altlvds_tx:altlvds_tx_component|lvds_tx_0rm:auto_generated|ddio_out_1j7:ddio_out
 14. Source assignments for rx:b2v_inst1|altlvds_rx:altlvds_rx_component
 15. Source assignments for sld_signaltap:auto_signaltap_0
 16. Source assignments for sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated
 17. Source assignments for sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr
 18. Source assignments for sld_hub:sld_hub_inst
 19. Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine
 20. Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG
 21. Parameter Settings for User Entity Instance: pll:bs2_pll|altpll:altpll_component
 22. Parameter Settings for User Entity Instance: tx:b2v_inst|altlvds_tx:altlvds_tx_component
 23. Parameter Settings for User Entity Instance: rx:b2v_inst1|altlvds_rx:altlvds_rx_component
 24. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
 25. Parameter Settings for Inferred Entity Instance: sld_hub:sld_hub_inst
 26. SignalTap II Logic Analyzer Settings
 27. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                          ;
+------------------------------------+--------------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Nov 07 03:09:18 2006            ;
; Quartus II Version                 ; 6.0 Build 202 06/20/2006 SP 1.18 SJ Full Version ;
; Revision Name                      ; lvds                                             ;
; Top-level Entity Name              ; lvds                                             ;
; Family                             ; Cyclone II                                       ;
; Total logic elements               ; 358                                              ;
; Total registers                    ; 358                                              ;