lvds.v

nios系统下LVDS的ip源码

// Copyright (C) 1991-2006 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
`timescale 1 ns / 1 ns
module lvds(
	rx_i,
	clk_i,
	tx_o,
	reset_n,
	data_reveive,
	tr_reg
);

input	rx_i;
input	clk_i;
output	tx_o;
reg rx_tx_en; 
input reset_n;
output [7:0] tr_reg;
reg [7:0] tr_reg;
reg tr_cnt;
output [7:0] data_reveive;
reg [7:0] data_reveive;

wire clk_25M;
wire clk_200M;
reg[1:0] clk_cnt;

 pll bs2_pll(
	.inclk0(clk_i),
	.c0(clk_25M),
	.c1(clk_200M)
	);

always@(posedge clk_25M or negedge reset_n)
begin
   if(~reset_n)
	begin
	 rx_tx_en <=0;
	tr_reg <= 8'h55;
	tr_cnt <=0;
	
	end
	else
	begin
	  rx_tx_en <=1;
		tr_reg <= tr_reg + 1'b1;
	end
	/*
	begin
	case(tr_cnt)
	0:
	begin
		rx_tx_en <=1;
		tr_reg <= 8'h55;
		tr_cnt <=1;	
	end
	1:
	begin
		rx_tx_en <=1;
		tr_reg <= 8'haa;
		tr_cnt <=0;	
	end
	endcase
	end
	*/
end


reg [7:0] tx_data;
always@(posedge clk_25M)//clk_200M
begin
//  	if(rx_tx_en ==1)
		tx_data <= tr_reg;
end

tx	b2v_inst(
.tx_in(tx_data),
.tx_inclock(clk_200M),
.tx_out(tx_o)
);


wire [7:0]data_out;
rx	b2v_inst1(
.rx_inclock(clk_200M),
.rx_in(rx_i),
.rx_out(data_out)
);


always@(posedge clk_25M or negedge reset_n)
begin
   if(~reset_n)
	begin
		data_reveive <=0;
	end
	else
	begin
		data_reveive <= data_out;
	end
end
endmodule