lvds.tan.summary

nios系统下LVDS的ip源码

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.984 ns
From           : reset_n
To             : sld_signaltap:auto_signaltap_0|acq_trigger_in_reg[9]
From Clock     : --
To Clock       : clk_i
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.236 ns
From           : data_reveive[2]~reg0
To             : data_reveive[2]
From Clock     : clk_i
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 3.106 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.411 ns
From           : altera_internal_jtag
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize|dffs[53]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum Pulse Width Requirement (Low)
Slack          : -0.567 ns
Required Time  : 3.067 ns
Actual Time    : 2.500 ns
From           : pll:bs2_pll|altpll:altpll_component|_clk1
To             : sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg0
From Clock     : --
To Clock       : --
Failed Paths   : 43

Type           : Worst-case Minimum Pulse Width Requirement (High)
Slack          : -0.567 ns
Required Time  : 3.067 ns
Actual Time    : 2.500 ns
From           : pll:bs2_pll|altpll:altpll_component|_clk1
To             : sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg0
From Clock     : --
To Clock       : --
Failed Paths   : 43

Type           : Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk1'
Slack          : N/A
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : Restricted to 163.03 MHz ( period = 6.134 ns )
From           : sld_signaltap:auto_signaltap_0|sld_acquisition_buffer:sld_acquisition_buffer_inst|lpm_counter:\write_address_non_zero_gen:write_pointer_counter|cntr_blh:auto_generated|safe_q[0]
To             : sld_signaltap:auto_signaltap_0|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_fri2:auto_generated|ram_block1a0~porta_datain_reg17
From Clock     : pll:bs2_pll|altpll:altpll_component|_clk1
To Clock       : pll:bs2_pll|altpll:altpll_component|_clk1
Failed Paths   : 75

Type           : Clock Setup: 'pll:bs2_pll|altpll:altpll_component|_clk0'
Slack          : 3.829 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : rx:b2v_inst1|altlvds_rx:altlvds_rx_component|lvds_rx_hin:auto_generated|shift_reg_4n5:shift_reg1|shift_reg[1]
To             : data_reveive[3]~reg0
From Clock     : pll:bs2_pll|altpll:altpll_component|_clk1
To Clock       : pll:bs2_pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 90.66 MHz ( period = 11.030 ns )
From           : sld_signaltap:auto_signaltap_0|sld_rom_sr:crc_rom_sr|WORD_SR[0]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll:bs2_pll|altpll:altpll_component|_clk0'
Slack          : 0.499 ns
Required Time  : 25.00 MHz ( period = 40.000 ns )
Actual Time    : N/A
From           : tr_reg[0]~reg0
To             : tr_reg[0]~reg0
From Clock     : pll:bs2_pll|altpll:altpll_component|_clk0
To Clock       : pll:bs2_pll|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Hold: 'pll:bs2_pll|altpll:altpll_component|_clk1'
Slack          : 0.499 ns
Required Time  : 200.00 MHz ( period = 5.000 ns )
Actual Time    : N/A
From           : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena
To             : sld_signaltap:auto_signaltap_0|sld_ela_control:ela_control|sld_ela_segment_mgr:\gen_non_zero_sample_depth_segment:seg_mgr|segment_write_addr_adv_ena
From Clock     : pll:bs2_pll|altpll:altpll_component|_clk1
To Clock       : pll:bs2_pll|altpll:altpll_component|_clk1
Failed Paths   : 0

Type           : Other violations (see messages)
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 1

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 162

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