dac908.v
来自「基于fpga」· Verilog 代码 · 共 33 行
V
33 行
module dac908(inclk,daclk,pd,out2dac908);
input inclk;
output[7:0] out2dac908;
output daclk;
output pd;
//reg[23:0] counter;
reg daclk;
reg[7:0] out2dac908;
reg[7:0]temp;
assign pd=1'b0;
//assign out2dac908 = 8'hFF;
always@(posedge inclk)
begin
//if(counter==24'd10)//24M/10
//begin
daclk=~daclk;
//counter<=24'b0;
//end
//else
//counter<=counter+1;
end
always@(negedge daclk)//here if posedge ,still have wave(why?)
begin
for(temp=8'b0;temp<8'd255;temp=temp+8'd1)
out2dac908<=out2dac908+8'b1;
end
endmodule
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