dds.hier_info

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clrn => sout_node[5].ACLR
clrn => sout_node[4].ACLR
clrn => sout_node[3].ACLR
clrn => sout_node[2].ACLR
clrn => sout_node[1].ACLR
clrn => sout_node[0].ACLR
ena => sout_node[6].ENA
ena => sout_node[5].ENA
ena => sout_node[4].ENA
ena => sout_node[3].ENA
ena => sout_node[2].ENA
ena => sout_node[1].ENA
ena => sout_node[0].ENA
sout[0] <= sout_node[0].DB_MAX_OUTPUT_PORT_TYPE
sout[1] <= sout_node[1].DB_MAX_OUTPUT_PORT_TYPE
sout[2] <= sout_node[2].DB_MAX_OUTPUT_PORT_TYPE
sout[3] <= sout_node[3].DB_MAX_OUTPUT_PORT_TYPE
sout[4] <= sout_node[4].DB_MAX_OUTPUT_PORT_TYPE
sout[5] <= sout_node[5].DB_MAX_OUTPUT_PORT_TYPE
sout[6] <= sout_node[6].DB_MAX_OUTPUT_PORT_TYPE
cout[0] <= cout[0]~6.DB_MAX_OUTPUT_PORT_TYPE
cout[1] <= cout[1]~5.DB_MAX_OUTPUT_PORT_TYPE
cout[2] <= cout[2]~4.DB_MAX_OUTPUT_PORT_TYPE
cout[3] <= cout[3]~3.DB_MAX_OUTPUT_PORT_TYPE
cout[4] <= cout[4]~2.DB_MAX_OUTPUT_PORT_TYPE
cout[5] <= cout[5]~1.DB_MAX_OUTPUT_PORT_TYPE
cout[6] <= cout[6]~0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
d[0] => q[0].DATAIN
d[1] => q[1].DATAIN
d[2] => q[2].DATAIN
d[3] => q[3].DATAIN
d[4] => q[4].DATAIN
d[5] => q[5].DATAIN
d[6] => q[6].DATAIN
clk => ~NO_FANOUT~
clrn => ~NO_FANOUT~
ena => ~NO_FANOUT~
q[0] <= d[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= d[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= d[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= d[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= d[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= d[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= d[6].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
d[0] => ffs[0].DATAIN
d[1] => ffs[1].DATAIN
clk => ffs[1].CLK
clk => ffs[0].CLK
clrn => ffs[1].ACLR
clrn => ffs[0].ACLR
ena => ffs[1].ENA
ena => ffs[0].ENA
q[0] <= ffs[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= ffs[1].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
data[0] => result[0].DATAIN
data[1] => result[1].DATAIN
data[2] => result[2].DATAIN
data[3] => result[3].DATAIN
data[4] => result[4].DATAIN
data[5] => result[5].DATAIN
data[6] => result[6].DATAIN
data[7] => result[7].DATAIN
data[8] => result[8].DATAIN
data[9] => result[9].DATAIN
data[10] => result[10].DATAIN
data[11] => result[11].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE
result[1] <= data[1].DB_MAX_OUTPUT_PORT_TYPE
result[2] <= data[2].DB_MAX_OUTPUT_PORT_TYPE
result[3] <= data[3].DB_MAX_OUTPUT_PORT_TYPE
result[4] <= data[4].DB_MAX_OUTPUT_PORT_TYPE
result[5] <= data[5].DB_MAX_OUTPUT_PORT_TYPE
result[6] <= data[6].DB_MAX_OUTPUT_PORT_TYPE
result[7] <= data[7].DB_MAX_OUTPUT_PORT_TYPE
result[8] <= data[8].DB_MAX_OUTPUT_PORT_TYPE
result[9] <= data[9].DB_MAX_OUTPUT_PORT_TYPE
result[10] <= data[10].DB_MAX_OUTPUT_PORT_TYPE
result[11] <= data[11].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|DDS|PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
data[0] => result[0].DATAIN
clock => ~NO_FANOUT~
aclr => ~NO_FANOUT~
clken => ~NO_FANOUT~
result[0] <= data[0].DB_MAX_OUTPUT_PORT_TYPE


|DDS|RAM256:inst3
Addr[0] => Mem__dual.RADDR
Addr[1] => Mem__dual.RADDR1
Addr[2] => Mem__dual.RADDR2
Addr[3] => Mem__dual.RADDR3
Addr[4] => Mem__dual.RADDR4
Addr[5] => Mem__dual.RADDR5
Addr[6] => Mem__dual.RADDR6
Addr[7] => Mem__dual.RADDR7
ALE => tempp0[6].CLK
ALE => tempp0[5].CLK
ALE => tempp0[4].CLK
ALE => tempp0[3].CLK
ALE => tempp0[2].CLK
ALE => tempp0[1].CLK
ALE => tempp0[0].CLK
ALE => tempp0[7].CLK
ALE => Mem.CLK1
WR => Mem.datain[6].CLK
WR => Mem.datain[5].CLK
WR => Mem.datain[4].CLK
WR => Mem.datain[3].CLK
WR => Mem.datain[2].CLK
WR => Mem.datain[1].CLK
WR => Mem.datain[0].CLK
WR => Mem.waddr[7].CLK
WR => Mem.waddr[6].CLK
WR => Mem.waddr[5].CLK
WR => Mem.waddr[4].CLK
WR => Mem.waddr[3].CLK
WR => Mem.waddr[2].CLK
WR => Mem.waddr[1].CLK
WR => Mem.waddr[0].CLK
WR => always1~0.CLK
WR => Mem.datain[7].CLK
WR => Mem.CLK0
WR => Mem__dual.CLK0
RD => P0~8.IN1
CS => P0~8.IN0
CS => always1~0.DATAIN
CS => Mem.WE
CS => Mem__dual.WE
P0[0] <= P0~16
P0[1] <= P0~15
P0[2] <= P0~14
P0[3] <= P0~13
P0[4] <= P0~12
P0[5] <= P0~11
P0[6] <= P0~10
P0[7] <= P0~9
EN => test~0.OE
EN => test~1.OE
EN => test~2.OE
EN => test~3.OE
EN => test~4.OE
EN => test~5.OE
EN => test~6.OE
EN => test~7.OE
EN => test~8.OE
EN => test~9.OE
EN => test~10.OE
EN => test~11.OE
test[0] <= test~11.DB_MAX_OUTPUT_PORT_TYPE
test[1] <= test~10.DB_MAX_OUTPUT_PORT_TYPE
test[2] <= test~9.DB_MAX_OUTPUT_PORT_TYPE
test[3] <= test~8.DB_MAX_OUTPUT_PORT_TYPE
test[4] <= test~7.DB_MAX_OUTPUT_PORT_TYPE
test[5] <= test~6.DB_MAX_OUTPUT_PORT_TYPE
test[6] <= test~5.DB_MAX_OUTPUT_PORT_TYPE
test[7] <= test~4.DB_MAX_OUTPUT_PORT_TYPE
test[8] <= test~3.DB_MAX_OUTPUT_PORT_TYPE
test[9] <= test~2.DB_MAX_OUTPUT_PORT_TYPE
test[10] <= test~1.DB_MAX_OUTPUT_PORT_TYPE
test[11] <= test~0.DB_MAX_OUTPUT_PORT_TYPE


|DDS|AddrCt:inst5
clock => lpm_counter:lpm_counter_component.clock
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]


|DDS|AddrCt:inst5|lpm_counter:lpm_counter_component
clock => cntr_adh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_adh:auto_generated.q[0]
q[1] <= cntr_adh:auto_generated.q[1]
q[2] <= cntr_adh:auto_generated.q[2]
q[3] <= cntr_adh:auto_generated.q[3]
q[4] <= cntr_adh:auto_generated.q[4]
q[5] <= cntr_adh:auto_generated.q[5]
q[6] <= cntr_adh:auto_generated.q[6]
q[7] <= cntr_adh:auto_generated.q[7]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|DDS|AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT


|DDS|ReadCt:inst4
clock => lpm_counter:lpm_counter_component.clock
cout <= lpm_counter:lpm_counter_component.cout
q[0] <= lpm_counter:lpm_counter_component.q[0]
q[1] <= lpm_counter:lpm_counter_component.q[1]
q[2] <= lpm_counter:lpm_counter_component.q[2]
q[3] <= lpm_counter:lpm_counter_component.q[3]
q[4] <= lpm_counter:lpm_counter_component.q[4]
q[5] <= lpm_counter:lpm_counter_component.q[5]
q[6] <= lpm_counter:lpm_counter_component.q[6]
q[7] <= lpm_counter:lpm_counter_component.q[7]


|DDS|ReadCt:inst4|lpm_counter:lpm_counter_component
clock => cntr_5sh:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => ~NO_FANOUT~
updown => ~NO_FANOUT~
aclr => ~NO_FANOUT~
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
data[6] => ~NO_FANOUT~
data[7] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_5sh:auto_generated.q[0]
q[1] <= cntr_5sh:auto_generated.q[1]
q[2] <= cntr_5sh:auto_generated.q[2]
q[3] <= cntr_5sh:auto_generated.q[3]
q[4] <= cntr_5sh:auto_generated.q[4]
q[5] <= cntr_5sh:auto_generated.q[5]
q[6] <= cntr_5sh:auto_generated.q[6]
q[7] <= cntr_5sh:auto_generated.q[7]
cout <= cntr_5sh:auto_generated.cout
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|DDS|ReadCt:inst4|lpm_counter:lpm_counter_component|cntr_5sh:auto_generated
clock => counter_cella0.CLK
clock => counter_cella1.CLK
clock => counter_cella2.CLK
clock => counter_cella3.CLK
clock => counter_cella4.CLK
clock => counter_cella5.CLK
clock => counter_cella6.CLK
clock => counter_cella7.CLK
cout <= cout_bit.COMBOUT
q[0] <= counter_cella0.REGOUT
q[1] <= counter_cella1.REGOUT
q[2] <= counter_cella2.REGOUT
q[3] <= counter_cella3.REGOUT
q[4] <= counter_cella4.REGOUT
q[5] <= counter_cella5.REGOUT
q[6] <= counter_cella6.REGOUT
q[7] <= counter_cella7.REGOUT