dds.fit.qmsg

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{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "13.753 ns register register " "Info: Estimated most critical path is register to register delay of 13.753 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns AddrCt:inst5\|lpm_counter:lpm_counter_component\|cntr_adh:auto_generated\|safe_q\[5\] 1 REG LAB_X15_Y11 254 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X15_Y11; Fanout = 254; REG Node = 'AddrCt:inst5\|lpm_counter:lpm_counter_component\|cntr_adh:auto_generated\|safe_q\[5\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5] } "NODE_NAME" } } { "db/cntr_adh.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/cntr_adh.tdf" 98 8 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.137 ns) + CELL(0.442 ns) 2.579 ns RAM256:inst3\|Mem__dual~67586 2 COMB LAB_X23_Y6 1 " "Info: 2: + IC(2.137 ns) + CELL(0.442 ns) = 2.579 ns; Loc. = LAB_X23_Y6; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67586'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.579 ns" { AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5] RAM256:inst3|Mem__dual~67586 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.575 ns) + CELL(0.590 ns) 4.744 ns RAM256:inst3\|Mem__dual~67587 3 COMB LAB_X27_Y11 1 " "Info: 3: + IC(1.575 ns) + CELL(0.590 ns) = 4.744 ns; Loc. = LAB_X27_Y11; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67587'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.165 ns" { RAM256:inst3|Mem__dual~67586 RAM256:inst3|Mem__dual~67587 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.923 ns) + CELL(0.442 ns) 6.109 ns RAM256:inst3\|Mem__dual~67590 4 COMB LAB_X26_Y14 1 " "Info: 4: + IC(0.923 ns) + CELL(0.442 ns) = 6.109 ns; Loc. = LAB_X26_Y14; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67590'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.365 ns" { RAM256:inst3|Mem__dual~67587 RAM256:inst3|Mem__dual~67590 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.374 ns) + CELL(0.292 ns) 7.775 ns RAM256:inst3\|Mem__dual~67593 5 COMB LAB_X23_Y13 1 " "Info: 5: + IC(1.374 ns) + CELL(0.292 ns) = 7.775 ns; Loc. = LAB_X23_Y13; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67593'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.666 ns" { RAM256:inst3|Mem__dual~67590 RAM256:inst3|Mem__dual~67593 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.153 ns) + CELL(0.114 ns) 9.042 ns RAM256:inst3\|Mem__dual~67594 6 COMB LAB_X26_Y13 1 " "Info: 6: + IC(1.153 ns) + CELL(0.114 ns) = 9.042 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67594'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.267 ns" { RAM256:inst3|Mem__dual~67593 RAM256:inst3|Mem__dual~67594 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.361 ns) + CELL(0.292 ns) 9.695 ns RAM256:inst3\|Mem__dual~67605 7 COMB LAB_X26_Y13 1 " "Info: 7: + IC(0.361 ns) + CELL(0.292 ns) = 9.695 ns; Loc. = LAB_X26_Y13; Fanout = 1; COMB Node = 'RAM256:inst3\|Mem__dual~67605'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.653 ns" { RAM256:inst3|Mem__dual~67594 RAM256:inst3|Mem__dual~67605 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.113 ns) + CELL(0.590 ns) 11.398 ns RAM256:inst3\|Mem__dual~67733 8 COMB LAB_X21_Y10 3 " "Info: 8: + IC(1.113 ns) + CELL(0.590 ns) = 11.398 ns; Loc. = LAB_X21_Y10; Fanout = 3; COMB Node = 'RAM256:inst3\|Mem__dual~67733'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.703 ns" { RAM256:inst3|Mem__dual~67605 RAM256:inst3|Mem__dual~67733 } "NODE_NAME" } } { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.622 ns) + CELL(0.564 ns) 12.584 ns PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~30 9 COMB LAB_X20_Y10 2 " "Info: 9: + IC(0.622 ns) + CELL(0.564 ns) = 12.584 ns; Loc. = LAB_X20_Y10; Fanout = 2; COMB Node = 'PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[2\]~30'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.186 ns" { RAM256:inst3|Mem__dual~67733 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.271 ns) 12.855 ns PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~31 10 COMB LAB_X20_Y10 3 " "Info: 10: + IC(0.000 ns) + CELL(0.271 ns) = 12.855 ns; Loc. = LAB_X20_Y10; Fanout = 3; COMB Node = 'PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[3\]~31'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.271 ns" { PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.898 ns) 13.753 ns PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\] 11 REG LAB_X20_Y10 11 " "Info: 11: + IC(0.000 ns) + CELL(0.898 ns) = 13.753 ns; Loc. = LAB_X20_Y10; Fanout = 11; REG Node = 'PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\|addcore:adder1\[0\]\|a_csnbuffer:result_node\|sout_node\[4\]'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.898 ns" { PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } } { "a_csnbuffer.tdf" "" { Text "d:/program files/altera/quartus60/libraries/megafunctions/a_csnbuffer.tdf" 34 13 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.495 ns ( 32.68 % ) " "Info: Total cell delay = 4.495 ns ( 32.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.258 ns ( 67.32 % ) " "Info: Total interconnect delay = 9.258 ns ( 67.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "13.753 ns" { AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5] RAM256:inst3|Mem__dual~67586 RAM256:inst3|Mem__dual~67587 RAM256:inst3|Mem__dual~67590 RAM256:inst3|Mem__dual~67593 RAM256:inst3|Mem__dual~67594 RAM256:inst3|Mem__dual~67605 RAM256:inst3|Mem__dual~67733 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[2]~30 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[3]~31 PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[4] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "27 52 " "Info: Average interconnect usage is 27% of the available device resources. Peak interconnect usage is 52%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "x12_y0 x23_y10 " "Info: The peak interconnect region extends from location x12_y0 to location x23_y10" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:08 " "Info: Fitter routing operations ending: elapsed time is 00:00:08" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "1 " "Warning: Following 1 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "PD GND " "Info: Pin PD has GND driving its datain port" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 496 560 736 512 "PD" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "PD" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PD } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { PD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0}
{ "Info" "IFIOMGR_ALL_OUTPUT_ENABLE_GROUPS" "" "Info: Following groups of pins have the same output enable" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP" "RAM256:inst3\|P0~8 " "Info: Following pins have the same output enable: RAM256:inst3\|P0~8" { { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[7\] LVTTL " "Info: Type bidirectional pin P0\[7\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[7\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[7] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[7] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[5\] LVTTL " "Info: Type bidirectional pin P0\[5\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[5\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[5] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[5] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[3\] LVTTL " "Info: Type bidirectional pin P0\[3\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[3\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[3] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[3] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[1\] LVTTL " "Info: Type bidirectional pin P0\[1\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[1\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[1] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[1] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[6\] LVTTL " "Info: Type bidirectional pin P0\[6\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[6\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[6] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[6] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[4\] LVTTL " "Info: Type bidirectional pin P0\[4\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[4\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[4] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[4] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[2\] LVTTL " "Info: Type bidirectional pin P0\[2\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[2\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[2] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[2] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0} { "Info" "IFIOMGR_SAME_OUTPUT_ENABLE_GROUP_SUB" "bidirectional P0\[0\] LVTTL " "Info: Type bidirectional pin P0\[0\] uses the LVTTL I/O standard" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 120 336 512 136 "P0\[7..0\]" "" } } } } { "d:/program files/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "d:/program files/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "P0\[0\]" } } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[0] } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { P0[0] } "NODE_NAME" } }  } 0 0 "Type %1!s! pin %2!s! uses the %3!s! I/O standard" 0 0}  } {  } 0 0 "Following pins have the same output enable: %1!s!" 0 0}  } {  } 0 0 "Following groups of pins have the same output enable" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 13 10:30:40 2007 " "Info: Processing ended: Fri Jul 13 10:30:40 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:29 " "Info: Elapsed time: 00:00:29" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "D:/zx/quartus_project/dds/DDS/DDS.fit.smsg " "Info: Generated suppressed messages file D:/zx/quartus_project/dds/DDS/DDS.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}