dds.map.qmsg

基于ｆｐｇａ

{ "Info" "ISGN_MEGAFN_PARAM_TOP" "PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component " "Info: Instantiated megafunction \"PhaseAdd:inst1\|lpm_add_sub:lpm_add_sub_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_TYPE LPM_ADD_SUB " "Info: Parameter \"LPM_TYPE\" = \"LPM_ADD_SUB\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_HINT ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO " "Info: Parameter \"LPM_HINT\" = \"ONE_INPUT_IS_CONSTANT=NO,CIN_USED=NO\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTH 12 " "Info: Parameter \"LPM_WIDTH\" = \"12\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DIRECTION ADD " "Info: Parameter \"LPM_DIRECTION\" = \"ADD\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_PIPELINE 1 " "Info: Parameter \"LPM_PIPELINE\" = \"1\"" {  } {  } 0 0 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0}  } { { "PhaseAdd.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/PhaseAdd.tdf" 47 2 0 } }  } 0 0 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "RAM256 RAM256:inst3 " "Info: Elaborating entity \"RAM256\" for hierarchy \"RAM256:inst3\"" {  } { { "DDS.bdf" "inst3" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 184 472 624 344 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "AddrCt AddrCt:inst5 " "Info: Elaborating entity \"AddrCt\" for hierarchy \"AddrCt:inst5\"" {  } { { "DDS.bdf" "inst5" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 176 288 432 240 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter AddrCt:inst5\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"AddrCt:inst5\|lpm_counter:lpm_counter_component\"" {  } { { "AddrCt.tdf" "lpm_counter_component" { Text "D:/zx/quartus_project/dds/DDS/AddrCt.tdf" 44 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "AddrCt:inst5\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"AddrCt:inst5\|lpm_counter:lpm_counter_component\"" {  } { { "AddrCt.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/AddrCt.tdf" 44 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_adh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_adh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_adh " "Info: Found entity 1: cntr_adh" {  } { { "db/cntr_adh.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/cntr_adh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_adh AddrCt:inst5\|lpm_counter:lpm_counter_component\|cntr_adh:auto_generated " "Info: Elaborating entity \"cntr_adh\" for hierarchy \"AddrCt:inst5\|lpm_counter:lpm_counter_component\|cntr_adh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ReadCt ReadCt:inst4 " "Info: Elaborating entity \"ReadCt\" for hierarchy \"ReadCt:inst4\"" {  } { { "DDS.bdf" "inst4" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 232 192 272 376 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_counter ReadCt:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborating entity \"lpm_counter\" for hierarchy \"ReadCt:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "ReadCt.tdf" "lpm_counter_component" { Text "D:/zx/quartus_project/dds/DDS/ReadCt.tdf" 45 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "ReadCt:inst4\|lpm_counter:lpm_counter_component " "Info: Elaborated megafunction instantiation \"ReadCt:inst4\|lpm_counter:lpm_counter_component\"" {  } { { "ReadCt.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/ReadCt.tdf" 45 2 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_5sh.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cntr_5sh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_5sh " "Info: Found entity 1: cntr_5sh" {  } { { "db/cntr_5sh.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/cntr_5sh.tdf" 25 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_5sh ReadCt:inst4\|lpm_counter:lpm_counter_component\|cntr_5sh:auto_generated " "Info: Elaborating entity \"cntr_5sh\" for hierarchy \"ReadCt:inst4\|lpm_counter:lpm_counter_component\|cntr_5sh:auto_generated\"" {  } { { "lpm_counter.tdf" "auto_generated" { Text "d:/program files/altera/quartus60/libraries/megafunctions/lpm_counter.tdf" 257 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[11\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[11\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[10\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[10\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[9\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[9\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[8\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[8\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[7\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[7\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[6\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[6\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[5\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[5\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[4\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[4\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[3\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[3\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[2\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[2\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[1\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[1\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "RAM256:inst3\|test\[0\] " "Warning: Converting TRI node \"RAM256:inst3\|test\[0\]\" that feeds logic to a wire" {  } { { "RAM256.v" "" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 5 -1 0 } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Warning" "WOPT_RAM_FUNCTIONALITY_CHANGE_ALTSYNCRAM_DUAL_CLOCK" "RAM256:inst3\|Mem~0 " "Warning: Created node \"RAM256:inst3\|Mem~0\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." {  } { { "RAM256.v" "Mem~0" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "Created node \"%1!s!\" as a dual-clock RAM by generating altsyncram megafunction to implement register logic with M512 or M4K memory block or M-RAM. Functionality differs from the original design." 0 0}
{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_ALTSYNCRAM_INFERRED" "RAM256:inst3\|Mem~0 256 8 " "Info: Inferred altsyncram megafunction (NUMWORDS_A=256, WIDTH_A=8) from the following design logic: \"RAM256:inst3\|Mem~0\"" {  } { { "RAM256.v" "Mem~0" { Text "D:/zx/quartus_project/dds/DDS/RAM256.v" 7 -1 0 } }  } 0 0 "Inferred altsyncram megafunction (NUMWORDS_A=%2!d!, WIDTH_A=%3!d!) from the following design logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "RAM256:inst3\|altsyncram:Mem_rtl_0 " "Info: Elaborated megafunction instantiation \"RAM256:inst3\|altsyncram:Mem_rtl_0\"" {  } {  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hle1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_hle1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hle1 " "Info: Found entity 1: altsyncram_hle1" {  } { { "db/altsyncram_hle1.tdf" "" { Text "D:/zx/quartus_project/dds/DDS/db/altsyncram_hle1.tdf" 36 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "PD GND " "Warning: Pin \"PD\" stuck at GND" {  } { { "DDS.bdf" "" { Schematic "D:/zx/quartus_project/dds/DDS/DDS.bdf" { { 496 560 736 512 "PD" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "3784 " "Info: Implemented 3784 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "6 " "Info: Implemented 6 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "3744 " "Info: Implemented 3744 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_RAMS" "16 " "Info: Implemented 16 RAM segments" {  } {  } 0 0 "Implemented %1!d! RAM segments" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 18 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Jul 13 10:30:09 2007 " "Info: Processing ended: Fri Jul 13 10:30:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:21 " "Info: Elapsed time: 00:00:21" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}