dds.hif

基于ｆｐｇａ

}
# used_port {
sout6
-1
3
sout5
-1
3
sout4
-1
3
sout3
-1
3
sout2
-1
3
sout1
-1
3
sout0
-1
3
sin6
-1
3
sin5
-1
3
sin4
-1
3
sin3
-1
3
sin2
-1
3
sin1
-1
3
sin0
-1
3
ena
-1
3
cout6
-1
3
cout5
-1
3
cout4
-1
3
cout3
-1
3
cout2
-1
3
cout1
-1
3
cout0
-1
3
clrn
-1
3
clk
-1
3
cin6
-1
3
cin5
-1
3
cin4
-1
3
cin3
-1
3
cin2
-1
3
cin1
-1
3
cin0
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:result_node
}
# end
# entity
a_csnbuffer
# storage
db|DDS.(12).cnf
db|DDS.(12).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|a_csnbuffer.tdf
14fa1fe880ca66e7782a2fafd457197
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
NEED_CARRY
0
PARAMETER_UNKNOWN
DEF
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
}
# used_port {
sout0
-1
3
sin0
-1
3
ena
-1
3
clrn
-1
3
clk
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:cout_node
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]|a_csnbuffer:cout_node
}
# end
# entity
addcore
# storage
db|DDS.(13).cnf
db|DDS.(13).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|addcore.tdf
a63b3f9948676dba45ce9d3335c98e4
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
width
7
PARAMETER_UNKNOWN
USR
REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
DIRECTION
ADD
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
}
# used_port {
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result1
-1
3
result0
-1
3
datab5
-1
3
datab4
-1
3
datab3
-1
3
datab2
-1
3
datab1
-1
3
datab0
-1
3
dataa5
-1
3
dataa4
-1
3
dataa3
-1
3
dataa2
-1
3
dataa1
-1
3
dataa0
-1
3
clock
-1
3
clken
-1
3
aclr
-1
3
}
# include_file {
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|addcore.inc
ff795e21e4847824c03218724f1a1252
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|a_csnbuffer.inc
49de46f6a395e2e6edecabe6eac9d873
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1_0[1]
}
# end
# entity
bypassff
# storage
db|DDS.(14).cnf
db|DDS.(14).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][1]
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[1][0]
}
# end
# entity
bypassff
# storage
db|DDS.(15).cnf
db|DDS.(15).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
7
PARAMETER_UNKNOWN
USR
}
# used_port {
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
d6
-1
3
d5
-1
3
d4
-1
3
d3
-1
3
d2
-1
3
d1
-1
3
d0
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][1]
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:datab1_ff[0][0]
}
# end
# entity
bypassff
# storage
db|DDS.(16).cnf
db|DDS.(16).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|bypassff.tdf
5a3ffc33a19f67d4f5edca6ceea08d60
6
# user_parameter {
WIDTH
2
PARAMETER_UNKNOWN
USR
}
# used_port {
q1
-1
3
q0
-1
3
ena
-1
3
d1
-1
3
d0
-1
3
clrn
-1
3
clk
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|bypassff:sign_ff[0]
}
# end
# entity
altshift
# storage
db|DDS.(17).cnf
db|DDS.(17).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|altshift.tdf
eedda481b22c659bfdc3e0a628220
6
# user_parameter {
WIDTH
12
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result9
-1
3
result8
-1
3
result7
-1
3
result6
-1
3
result5
-1
3
result4
-1
3
result3
-1
3
result2
-1
3
result11
-1
3
result10
-1
3
result1
-1
3
result0
-1
3
data9
-1
3
data8
-1
3
data7
-1
3
data6
-1
3
data5
-1
3
data4
-1
3
data3
-1
3
data2
-1
3
data11
-1
3
data10
-1
3
data1
-1
3
data0
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:result_ext_latency_ffs
}
# end
# entity
altshift
# storage
db|DDS.(18).cnf
db|DDS.(18).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|altshift.tdf
eedda481b22c659bfdc3e0a628220
6
# user_parameter {
WIDTH
1
PARAMETER_UNKNOWN
USR
DEPTH
0
PARAMETER_UNKNOWN
USR
}
# used_port {
result0
-1
3
data0
-1
3
}
# hierarchies {
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:carry_ext_latency_ffs
PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|altshift:oflow_ext_latency_ffs
}
# end
# entity
AddrCt
# storage
db|DDS.(20).cnf
db|DDS.(20).cnf
# case_insensitive
# source_file
AddrCt.tdf
f72d6ef1c71b38f4c5b8d543ab820a0
6
# used_port {
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# include_file {
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
}
# hierarchies {
AddrCt:inst5
}
# end
# entity
lpm_counter
# storage
db|DDS.(21).cnf
db|DDS.(21).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_counter.tdf
9ee47257a6b8b166152317b4e89afa
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
8
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
0
PARAMETER_UNKNOWN
DEF
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_adh
PARAMETER_UNKNOWN
USR
}
# used_port {
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# include_file {
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_synch_counter.inc
e64d362a7450ad9895aa7e1e5dc2b42a
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_synch_counter_f.inc
88e2e3ac71decf106c8d913bf441832f
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_counter_f10ke.inc
d8a92a43831e9df2804dcf9a927e20
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_counter_stratix.inc
587bf41cd15486161ec3eb5a1fef4c2
}
# hierarchies {
AddrCt:inst5|lpm_counter:lpm_counter_component
}
# end
# entity
cntr_adh
# storage
db|DDS.(22).cnf
db|DDS.(22).cnf
# case_insensitive
# source_file
db|cntr_adh.tdf
423a17a9461d1fe1d6bf2eed3f4564
6
# used_port {
q7
-1
3
q6
-1
3
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
clock
-1
3
}
# hierarchies {
AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated
}
# end
# entity
lpm_counter
# storage
db|DDS.(24).cnf
db|DDS.(24).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_counter.tdf
9ee47257a6b8b166152317b4e89afa
6
# user_parameter {
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
LPM_WIDTH
6
PARAMETER_UNKNOWN
USR
LPM_DIRECTION
UP
PARAMETER_UNKNOWN
USR
LPM_MODULUS
48
PARAMETER_UNKNOWN
USR
LPM_AVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_SVALUE
UNUSED
PARAMETER_UNKNOWN
DEF
LPM_PORT_UPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN
USR
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
NOT_GATE_PUSH_BACK
ON
NOT_GATE_PUSH_BACK
USR
CARRY_CNT_EN
SMART
PARAMETER_UNKNOWN
DEF
LABWIDE_SCLR
ON
PARAMETER_UNKNOWN
DEF
USE_NEW_VERSION
TRUE
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
cntr_t7j
PARAMETER_UNKNOWN
USR
}
# used_port {
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cout
-1
3
clock
-1
3
}
# include_file {
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_counter.inc
758886b0947dd67e65ec58adda9b948
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_decode.inc
bd0e2f5e01c1bd360461dceb53d48
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|aglobal60.inc
b3d07c643dae10ab2b3e646e99ec45fc
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_add_sub.inc
7d9a33dd39f13aa690c3d0edd88351
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|cmpconst.inc
e61874547688138e6fc0b49ff8760
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_constant.inc
dcde44eee59335c1e2fe75d574f9646
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|lpm_compare.inc
aec4ea1b78f4cda1c3effe18f1abbf63
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|dffeea.inc
55d29d20f7e852c37746bec4e2495ec
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_synch_counter.inc
e64d362a7450ad9895aa7e1e5dc2b42a
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_synch_counter_f.inc
88e2e3ac71decf106c8d913bf441832f
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_counter_f10ke.inc
d8a92a43831e9df2804dcf9a927e20
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|alt_counter_stratix.inc
587bf41cd15486161ec3eb5a1fef4c2
}
# end
# entity
cntr_t7j
# storage
db|DDS.(25).cnf
db|DDS.(25).cnf
# case_insensitive
# source_file
db|cntr_t7j.tdf
675bc47e076155ad09e5373205547bc
6
# used_port {
q5
-1
3
q4
-1
3
q3
-1
3
q2
-1
3
q1
-1
3
q0
-1
3
cout
-1
3
clock
-1
3
}
# end
# entity
altsyncram
# storage
db|DDS.(26).cnf
db|DDS.(26).cnf
# case_insensitive
# source_file
..|..|..|..|program files|altera|quartus60|libraries|megafunctions|altsyncram.tdf
c9a54fc8e33741c15b27e3d74d615aff
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
8
PARAMETER_UNKNOWN
USR
WIDTHAD_A
8
PARAMETER_UNKNOWN
USR
NUMWORDS_A
256
PARAMETER_UNKNOWN
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
8
PARAMETER_UNKNOWN
USR
WIDTHAD_B
8
PARAMETER_UNKNOWN
USR
NUMWORDS_B
256
PARAMETER_UNKNOWN
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
DONT_CARE
PARAMETER_UNKNOWN
DEF
INIT_FILE