ram256.v

来自「基于ｆｐｇａ」· Verilog 代码 · 共 28 行

module RAM256(Addr,ALE,WR,RD,CS,P0,EN,test);
	input ALE,WR,RD,CS,EN;
	input [7:0] Addr;
	inout [7:0] P0;
	output [11:0] test;
	reg [7:0] tempp0;
	reg [7:0] Mem[255:0];
	
	//reg [7:0] P0;
	
	
	always @(negedge ALE)
		begin
			tempp0 = P0;
		end
		
	always @(posedge WR)
		begin
			if(!CS)
				begin
					Mem[tempp0] = P0;
				end
		end
		

	assign P0 = (!(RD || CS)) ? Mem[tempp0] : 8'bzzzzzzzz ;
	assign test = (!EN)? {4'b00,Mem[Addr]}:12'bzzzzzzzzzzzz;
endmodule