dds.tan.rpt

基于ｆｐｇａ

+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 9.410 ns                         ; CS                                                                                                           ; RAM256:inst3|Mem__dual~3974                                                                             ; --         ; WR       ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 19.796 ns                        ; ROM4096:inst|altsyncram:altsyncram_component|altsyncram_ji31:auto_generated|ram_block1a6~porta_address_reg11 ; DAOUT[6]                                                                                                ; fpgaclk    ; --       ; 0            ;
; Worst-case tpd               ; N/A   ; None          ; 15.359 ns                        ; RD                                                                                                           ; P0[0]                                                                                                   ; --         ; --       ; 0            ;
; Worst-case th                ; N/A   ; None          ; 0.832 ns                         ; P0[4]                                                                                                        ; RAM256:inst3|Mem__dual~2736                                                                             ; --         ; WR       ; 0            ;
; Clock Setup: 'fpgaclk'       ; N/A   ; None          ; 64.95 MHz ( period = 15.397 ns ) ; AddrCt:inst5|lpm_counter:lpm_counter_component|cntr_adh:auto_generated|safe_q[5]                             ; PhaseAdd:inst1|lpm_add_sub:lpm_add_sub_component|addcore:adder1[0]|a_csnbuffer:result_node|sout_node[6] ; fpgaclk    ; fpgaclk  ; 0            ;
; Clock Setup: 'WR'            ; N/A   ; None          ; 197.01 MHz ( period = 5.076 ns ) ; RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_datain_reg7              ; RAM256:inst3|altsyncram:Mem_rtl_0|altsyncram_hle1:auto_generated|ram_block1a7~porta_memory_reg7         ; WR         ; WR       ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                                                                                                              ;                                                                                                         ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+--------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C6Q240C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                         ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; fpgaclk         ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; WR              ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; ALE             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;