dds.st

基于ｆｐｇａ

          <wire connection_status="true" name="PhaseAdd:inst1|result[10]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[11]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[8]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="PhaseAdd:inst1|result[9]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|Addr[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[0]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[10]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[11]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[1]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[2]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[3]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[4]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[5]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[6]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[7]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[8]" tap_mode="classic" type="combinatorial"/>
          <wire connection_status="true" name="RAM256:inst3|test[9]" tap_mode="classic" type="combinatorial"/>
        </data_input_vec>
      </signal_vec>
      <presentation>
        <data_view>
          <bus is_signal_inverted="no" link="all" name="DAOUT" order="msb_to_lsb" radix="line" state="collapse" type="output pin">
            <net is_signal_inverted="no" name="DAOUT[7]"/>
            <net is_signal_inverted="no" name="DAOUT[6]"/>
            <net is_signal_inverted="no" name="DAOUT[5]"/>
            <net is_signal_inverted="no" name="DAOUT[4]"/>
            <net is_signal_inverted="no" name="DAOUT[3]"/>
            <net is_signal_inverted="no" name="DAOUT[2]"/>
            <net is_signal_inverted="no" name="DAOUT[1]"/>
            <net is_signal_inverted="no" name="DAOUT[0]"/>
          </bus>
          <net is_signal_inverted="no" name="EN"/>
          <bus is_signal_inverted="no" link="all" name="PhaseAdd:inst1|dataa" order="msb_to_lsb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[11]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[10]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[9]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[8]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[7]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[6]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[5]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[4]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[3]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[2]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[1]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|dataa[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="PhaseAdd:inst1|datab" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[11]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[10]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[9]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[8]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[7]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[6]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[5]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[4]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[3]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[2]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[1]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|datab[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="PhaseAdd:inst1|result" order="msb_to_lsb" radix="line" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[11]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[10]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[9]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[8]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[7]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[6]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[5]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[4]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[3]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[2]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[1]"/>
            <net is_signal_inverted="no" name="PhaseAdd:inst1|result[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="RAM256:inst3|Addr" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[7]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[6]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[5]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[4]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[3]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[2]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[1]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|Addr[0]"/>
          </bus>
          <bus is_signal_inverted="no" link="all" name="RAM256:inst3|test" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
            <net is_signal_inverted="no" name="RAM256:inst3|test[11]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[10]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[9]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[8]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[7]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[6]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[5]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[4]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[3]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[2]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[1]"/>
            <net is_signal_inverted="no" name="RAM256:inst3|test[0]"/>
          </bus>
        </data_view>